Tim15 Registers; Tim15 Control Register 1 (Tim15_Cr1) - STMicroelectronics STM32F05 series Reference Manual

General-purpose timers (TIM15/16/17)
18.5

TIM15 registers

Refer to
18.5.1

TIM15 control register 1 (TIM15_CR1)

Address offset: 0x00
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:10
Bits 9:8 CKD[1:0]: Clock division
Bit 7 ARPE: Auto-reload preload enable
Bits 6:4
Bit 3 OPM: One-pulse mode
Bit 2 URS: Update request source
Bit 1 UDIS: Update disable
402/742
Section 1.1 on page 34
12 11 10 9
Res. Res. CKD[1:0]
rw
Reserved, always read as 0.
This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (t
(TIx)
00: t = t
DTS CK_INT
01: t = 2*t
DTS CK_INT
10: t = 4*t
DTS CK_INT
11: Reserved, do not program this value
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Reserved, always read as 0.
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt if enabled. These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt if enabled
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
Doc ID 018940 Rev 1
for a list of abbreviations used in register descriptions.
8 7 6
ARPE Res.
rw rw
) used by the dead-time generators and the digital filters
DTS
5 4 3 2
Res. Res. OPM URS
rw rw
RM0091
1 0
UDIS CEN
rw rw