STMicroelectronics STM32F05 series Reference Manual page 520

Inter-integrated circuit (I
Bit 20 SMBHEN: SMBus Host address enable
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Bit 19 GCEN: General call enable
Bit 18 WUPEN: Wakeup from STOP enable
Note: If the Wakeup from STOP feature is not supported, this bit is reserved and forced by
Bit 17 NOSTRETCH: Clock stretching disable
Note: This bit can only be programmed when the I2C is disabled (PE = 0).
Bit 16 SBC: Slave byte control
Bit 15 RXDMAEN: DMA reception requests enable
Bit 14 TXDMAEN: DMA transmission requests enable
Bit 13 SWRST: Software reset
Note: This bit is write only, and is always read at '0'. Writing '0' has no effect.
Bit 12 ANFOFF: Analog noise filter OFF
Note: This bit can only be programmed when the I2C is disabled (PE = 0).
Bits 11:8 DNF[3:0]: Digital noise filter
Note: If the analog filter is also enabled, the digital filter is added to the analog filter.
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C) interface
0: Host address disabled. Address 0b0001000x is NACKed.
1: Host address enabled. Address 0b0001000x is ACKed.
Please refer to Section 23.3: I2C
0: General call disabled. Address 0b00000000 is NACKed.
1: General call enabled. Address 0b00000000 is ACKed.
0: Wakeup from STOP disable.
1: Wakeup from STOP enable.
hardware to '0'. Please refer to
This bit is used to disable clock stretching in slave mode.
0: Clock stretching enabled
1: Clock stretching disabled
This bit is used to enable hardware byte control in slave mode.
0: Slave byte control disabled
1: Slave byte control enabled
0: DMA mode disabled for reception
1: DMA mode enabled for reception
0: DMA mode disabled for transmission
1: DMA mode enabled for transmission
When set, the I2C SCL and SDA lines are released. Internal state machines and all status
bits are put back to their reset value. The content of configuration control bits is kept.
0: Analog noise filter enabled
1: Analog noise filter disabled
These bits are used to configure the digital noise filter on SDA and SCL input. The digital
filter will filter spikes with a length of up to DNF[3:0] * t
0000: Digital filter disabled
0001: Digital filter enabled and filtering capability up to 1 t
...
1111: digital filter enabled and filtering capability up to15 t
This filter can only be programmed when the I2C is disabled (PE = 0).
Doc ID 018940 Rev 1
implementation.
Section 23.3: I2C implementation.
I2CCLK
I2CCLK
I2CCLK
RM0091