Spi Error Flags - STMicroelectronics STM32F05 series Reference Manual

RM0091
Rx buffer not empty (RXNE)
The RXNE flag is set depending on the FRXTH bit value in the SPIx_CR2 register:
●
If FRXTH is set, RXNE goes high and stays high until the RXFIFO level is greater or
equal to 1/4 (8-bit).
●
If FRXTH is cleared, RXNE goes high and stays high until the RXFIFO level is greater
than or equal to 1/2 (16-bit).
An interrupt can be generated if the RXNEIE bit in the SPIx_CR2 register is set.
The RXNE is cleared by hardware automatically when the above conditions are no longer
true.
Busy flag (BSY)
The BSY flag is set and cleared by hardware (writing to this flag has no effect).
When BSY is set, it indicates that a data transfer is in progress on the SPI (the SPI bus is
busy).
The BSY flag can be used in certain modes to detect the end of a transfer so that the
software can disable the SPI or its peripheral clock before entering Halt mode. This avoids
corrupting the last transfer.
The BSY flag is also useful for preventing write collisions in a multimaster system.
The BSY flag is cleared under any one of the following conditions:
●
When the SPI is correctly disabled
●
When a fault is detected in Master mode (MODF bit set to 1)
●
In Master mode, when it finishes a data transmission and no new data is ready to be
sent
●
In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
each data transfer.
Note: When the next transmission can be handled immediately by the master (e.g. if the master is
in Receive-only mode or its Transmit FIFO is not empty), communication is continuous and
the BSY flag remains set to '1' between transfers on the master side. Although this is not the
case with a slave, it is recommended to use always the TXE and RXNE flags (instead of the
BSY flags) to handle data transmission or reception operations.
26.3.9

SPI error flags

An SPI interrupt is generated if one of the following error flags is set and interrupt is enabled
by setting the ERRIE bit.
Overrun flag (OVR)
An overrun condition occurs when either the master or the slave receiver has not cleared the
RXNE bit resulting from the previous transactions. An overrun condition occurs when data is
received when the RXFIFO has not enough space to store this received data. It can happen
if the software or the DMA did not have enough time to read previous received data stored in
the RXFIFO and free sufficient space for the next data to come. This could happen for
example when CRC is enabled, because in this case, the RXFIFO is not available and the
reception buffer is considered as a single buffer (see
Serial peripheral interface / inter-IC sound (SPI/I2S)
Doc ID 018940 Rev 1
Section 26.4.3: CRC calculation).
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