STMicroelectronics STM32F05 series Reference Manual page 712

HDMI-CEC controller (HDMI-CEC)
Bit 6 LBPEGEN: Generate Error-Bit on Long Bit Period Error
The LBPEGEN bit is set and cleared by software.
0: LBPE detection does not generate an Error-Bit on the CEC line
1: LBPE detection generates an Error-Bit on the CEC line
Note: If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if
LBPEGEN=0
Bit 5 BREGEN: Generate Error-Bit on Bit Rising Error
The BREGEN bit is set and cleared by software.
0: BRE detection does not generate an Error-Bit on the CEC line
1: BRE detection generates an Error-Bit on the CEC line (if BRESTP is set)
Note: If BRDNOGEN=0, an Error-bit is generated upon BRE detection with BRESTP=1 in broadcast
even if BREGEN=0
Bit 4 BRESTP: Rx-Stop on Bit Rising Error
The BRESTP bit is set and cleared by software.
0: BRE detection does not stop reception of the CEC message. Data bit is sampled at 1.05 ms.
1: BRE detection stops message reception
Bit 3 RXTOL: Rx-Tolerance
The RXTOL bit is set and cleared by software.
0: Standard tolerance margin:
–
–
1: Extended Tolerance
–
–
Bits [2:0] SFT: Signal Free Time
SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods
waited before transmission is ruled by hardware according to the transmission history. In all the other
configurations the SFT number is determined by software.
●
0x0
–
–
–
●
0x1: 0.5 nominal data bit periods
●
0x2: 1.5 nominal data bit periods
●
0x3: 2.5 nominal data bit periods
●
0x4: 3.5 nominal data bit periods
●
0x5: 4.5 nominal data bit periods
●
0x6: 5.5 nominal data bit periods
●
0x7: 6.5 nominal data bit periods
712/742
Start-Bit, +/- 200 µs rise, +/- 200 µs fall.
Data-Bit: +/- 200 µs rise. +/- 350 µs fall.
Start-Bit: +/- 400 µs rise, +/- 400 µs fall
Data-Bit: +/-300 µs rise, +/- 500 µs fall
2.5 Data-Bit periods if CEC is the last bus initiator with unsuccessful transmission
(ARBLST=1, TXERR=1, TXUDR=1 or TXACKE= 1)
4 Data-Bit periods if CEC is the new bus initiator
6 Data-Bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1)
Doc ID 018940 Rev 1
RM0091