Power Control Registers; Power Control Register (Pwr_Cr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
6.4

Power control registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
6.4.1

Power control register (PWR_CR)

Address offset: 0x00
Reset value: 0x0000 0000 (reset by wakeup from Standby mode)
31 30 29
Res Res Res
15 14 13
Res Res Res
Bits 31:9 Reserved, must be kept at reset value..
Bit 8 DBP: Disable backup domain write protection.
In reset state, the RTC and backup registers are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC and Backup registers disabled
1: Access to RTC and Backup registers enabled
Bits 7:5 PLS[2:0]: PVD level selection.
These bits are written by software to select the voltage threshold detected by the Power
Voltage Detector.
Once the PVD_LOCK is enabled in the
the PLS[2:0] bits cannot be programmed anymore.
000: PVD threshold 0
001: PVD threshold 1
010: PVD threshold 2
011: PVD threshold 3
100: PVD threshold 4
101: PVD threshold 5
110: PVD threshold 6
111: PVD threshold 7
Refer to the electrical characteristics of the datasheet for more details.
Bit 4 PVDE: Power voltage detector enable.
This bit is set and cleared by software. Once the PVD_LOCK is enabled in the
configuration register 2 (SYSCFG_CFGR2)
anymore.
0: PVD disabled
1: PVD enabled
Bit 3 CSBF: Clear standby flag.
This bit is always read as 0.
0: No effect
1: Clear the SBF Standby Flag (write).
28 27 26 25
Res Res Res Res
12 11 10 9
Res Res Res Res
Doc ID 018940 Rev 1
24 23 22 21
Res Res Res Res
8 7 6 5
DBP PLS[2:0]
rw rw rw rw
SYSCFG configuration register 2
register, the PVDE bit cannot be programmed
Power control (PWR)
20 19 18 17
Res Res Res Res
4 3 2 1
PVDE CSBF CWUF PDDS
rw rc_w1 rc_w1 rw
(SYSCFG_CFGR2),
SYSCFG
16
Res
0
LPDS
rw
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