Tim6 Registers; Tim6 Control Register 1 (Tim6_Cr1) - STMicroelectronics STM32F05 series Reference Manual

RM0091
19.4

TIM6 registers

Refer to
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
19.4.1

TIM6 control register 1 (TIM6_CR1)

Address offset: 0x00
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:8 Reserved, always read as 0.
Bit 7 ARPE: Auto-reload preload enable
Bits 6:4 Reserved, always read as 0.
Bit 3 OPM: One-pulse mode
Bit 2 URS: Update request source
Bit 1 UDIS: Update disable
Bit 0 CEN: Counter enable
Note: Gated mode can work only if the CEN bit has been previously set by software. However
CEN is cleared automatically in one-pulse mode, when an update event occurs.
Section 1.1 on page 34
12 11 10 9
Res. Res. Res.
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit).
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generates an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if
a hardware reset is received from the slave mode controller.
0: Counter disabled
1: Counter enabled
trigger mode can set the CEN bit automatically by hardware.
Doc ID 018940 Rev 1
for a list of abbreviations used in register descriptions.
8 7 6
Res. ARPE Res.
rw
Basic timer (TIM6)
5 4 3 2
Res. Res. OPM URS
rw rw
1 0
UDIS CEN
rw rw
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