Tim2 And Tim3 Dma/Interrupt Enable Register; Tim3_Dier) - STMicroelectronics STM32F05 series Reference Manual

RM0091
16.4.4 TIM2 and TIM3 DMA/Interrupt enable register (TIM2_DIER and

TIM3_DIER)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
Res. TDE Res. CC4DE CC3DE CC2DE CC1DE
rw
Bit 15
Bit 14 TDE: Trigger DMA request enable
Bit 13
Bit 12 CC4DE: Capture/Compare 4 DMA request enable
Bit 11 CC3DE: Capture/Compare 3 DMA request enable
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
Bit 8 UDE: Update DMA request enable
Bit 7
Bit 6 TIE: Trigger interrupt enable
Bit 5
Bit 4 CC4IE: Capture/Compare 4 interrupt enable
Bit 3 CC3IE: Capture/Compare 3 interrupt enable
12 11 10 9
rw rw rw rw
Reserved, must be kept at reset value.
0: Trigger DMA request disabled.
1: Trigger DMA request enabled.
Reserved, always read as 0
0: CC4 DMA request disabled.
1: CC4 DMA request enabled.
0: CC3 DMA request disabled.
1: CC3 DMA request enabled.
0: CC2 DMA request disabled.
1: CC2 DMA request enabled.
0: CC1 DMA request disabled.
1: CC1 DMA request enabled.
0: Update DMA request disabled.
1: Update DMA request enabled.
Reserved, must be kept at reset value.
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
Reserved, must be kept at reset value.
0: CC4 interrupt disabled.
1: CC4 interrupt enabled.
0: CC3 interrupt disabled
1: CC3 interrupt enabled
Doc ID 018940 Rev 1
General-purpose timers (TIM2 and TIM3)
8 7 6 5
UDE Res. TIE Res.
rw rw
4 3 2
CC4IE CC3IE CC2IE CC1IE
rw rw rw rw
1 0
UIE
rw
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