Pll; Lse Clock; Lsi Clock - STMicroelectronics STM32F05 series Reference Manual

Reset and clock control (RCC)
7.2.3

PLL

The internal PLL can be used to multiply the HSI or HSE output clock frequency. Refer to
Figure 10
The PLL configuration (selection of the input clock, and multiplication factor) must be done
before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed.
To modify the PLL configuration, proceed as follows:
1. Disable the PLL by setting PLLON to 0.
2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
3. Change the desired parameter.
4. Enable the PLL again by setting PLLON to 1.
An interrupt can be generated when the PLL is ready, if enabled in the
register (RCC_CIR).
The PLL output frequency must be set in the range 16-48 MHz.
7.2.4

LSE clock

The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage of providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in
register (RCC_BDCR). The crystal oscillator driving strength can be changed at runtime
using the LSEDRV[1:0] bits in the
the best compromise between robustness and short start-up time on one side and low
power-consumption on the other.
The LSERDY flag in the
the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not
released until this bit is set by hardware. An interrupt can be generated if enabled in the
Clock interrupt register
External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the
control register
~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin can be used as
GPIO. See
7.2.5

LSI clock

The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent window watchdog (IWWDG) and RTC. The clock
frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to the
electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the
(RCC_CSR).
88/742
and Clock control register
Backup domain control register (RCC_BDCR)
(RCC_CIR).
(RCC_BDCR). The external clock signal (square, sinus or triangle) with
Figure 11.
Doc ID 018940 Rev 1
(RCC_CR).
Backup domain control register (RCC_BDCR)
RM0091
Clock interrupt
Backup domain control
to obtain
indicates whether
Backup domain
Control/status register