Table 48. Tim2 And Tim3 Internal Trigger Connection - STMicroelectronics STM32F05 series Reference Manual

General-purpose timers (TIM2 and TIM3)
Bits 2:0 SMS: Slave mode selection
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100).
Table 48.
Slave TIM
TIM2
TIM3
334/742
When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
000: Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal
clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
level.
010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode
checks the level of the trigger signal.
TIM2 and TIM3 internal trigger connection
ITR0 (TS = 000)
TIM1
TIM1
Doc ID 018940 Rev 1
ITR1 (TS = 001) ITR2 (TS = 010)
TIM15
TIM2
ITR3 (TS = 011)
TIM3 TIM14
TIM15 TIM14
RM0091