Rtc Shift Control Register (Rtc_Shiftr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
24.6.9

RTC shift control register (RTC_SHIFTR)

This register is write protected. The write access procedure is described in
write protection on page 540.
Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29
ADD1S Res. Res. Res.
w
15 14 13
Res.
w w
Bit 31 ADD1S: Add one second
0: No effect
1: Add one second to the clock/calendar
This bit is write only and is always read as zero. Writing to this bit has no effect when a shift
operation is pending (when SHPF=1, in RTC_ISR).
This function is intended to be used with SUBFS (see description below) in order to
effectively add a fraction of a second to the clock in an atomic operation.
Bits 31:15 Reserved, must be kept at reset value
Bits 14:0 SUBFS: Subtract a fraction of a second
These bits are write only and is always read as zero. Writing to this bit has no effect when a
shift operation is pending (when SHPF=1, in RTC_ISR).
The value which is written to SUBFS is added to the synchronous prescaler's counter. Since
this counter counts down, this operation effectively subtracts from (delays) the clock by:
A fraction of a second can effectively be added to the clock (advancing the clock) when the
ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:
Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be
28 27 26 25
Res. Res. Res.
12 11 10 9
w w w w
Delay (seconds) = SUBFS / ( PREDIV_S + 1 )
Advance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) .
sure that the shadow registers have been updated with the shifted time.
Doc ID 018940 Rev 1
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
SUBFS[14:0]
w w w w
Real-time clock (RTC)
RTC register
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
w w w w
16
Res.
0
w
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