Figure 282. Audio Sampling Frequency Definition; Figure 283. I 2 S Clock Generator Architecture - STMicroelectronics STM32F05 series Reference Manual

RM0091

Figure 282. Audio sampling frequency definition

When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.
Figure 283. I
I²SxCLK
1. Where x can be 2 or 3.
Figure 282
system clock.
The audio sampling frequency may be 192 KHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz, 22.05
kHz, 16 kHz, 11.025 kHz or 8 kHz (or any other value within this range). In order to reach
the desired frequency, the linear divider needs to be programmed according to the formulas
below:
When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):
f = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
S
f = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide
S
When the master clock is disabled (MCKOE bit cleared):
f = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide
S
f = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide
S
Table 92
Note: Other configurations are possible that allow optimum clock precision.
sampling point
F : audio sampling frequency
S
2
S clock generator architecture
8-bit linear
divider +
reshaping stage
I²SDIV[7:0]
ODD
presents the communication clock architecture. The I2Sx clock is always the
provides example precision values for different clock configurations.
Doc ID 018940 Rev 1
Serial peripheral interface / inter-IC sound (SPI/I2S)
16-or 32-bit 16-or 32-bit
left channel right channel
32- or 64-bits
F
S
Divider by 4
sampling point
MS30108V1
0
0
Div2
1
1
MCKOE
MS30109V1
MCK
CK
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