Option Byte Write Protection; Flash Interrupts; Flash Register Description; Table 7. Flash Interrupt Request - STMicroelectronics STM32F05 series Reference Manual

Embedded Flash memory
If a program or an erase operation is performed on a protected sector, the Flash memory
returns a WRPRTERR protection error flag in the Flash memory Status Register
(FLASH_SR).
Write unprotection
To disable the write protection, two application cases are provided:
●
Case 1: Read protection disabled after the write unprotection:
–
–
–
●
Case 2: Read protection maintained active after the write unprotection, useful for in-
application programming with a user boot loader:
–
–
3.3.3

Option byte write protection

The option bytes are always read-accessible and write-protected by default. To gain write
access (Program/Erase) to the option bytes, a sequence of keys (same as for lock) has to
be written into the OPTKEYR. A correct sequence of keys gives write access to the option
bytes and this is indicated by OPTWRE in the FLASH_CR register being set. Write access
can be disabled by resetting the bit through software.
3.4

Flash interrupts

Table 7.
Interrupt event
End of operation
Write protection error
Programming error
3.5

Flash register description

The Flash memory registers have to be accessed by 32-bit words (half-word and byte
accesses are not allowed).
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Erase the entire option byte area by using the OPTER bit in the Flash memory
control register (FLASH_CR)
Program the code 0xAA in the RDP byte to unprotect the memory. This operation
forces a Mass Erase of the main Flash memory.
Set the OBL_LAUNCH bit in the Flash control register (FLASH_CR) to reload the
option bytes (and the new WRP[1:0] bytes), and to disable the write protection
Erase the entire option byte area by using the OPTER bit in the Flash memory
control register (FLASH_CR)
Set the OBL_LAUNCH bit in the Flash control register (FLASH_CR) to reload the
option bytes (and the new WRP[1:0] bytes), and to disable the write protection.
Flash interrupt request
Doc ID 018940 Rev 1
Event flag
EOP
WRPRTERR
PGERR
RM0091
Enable control bit
EOPIE
ERRIE
ERRIE