I2C2 Block Diagram; C Clock Requirements; Figure 196. I2C2 Block Diagram - STMicroelectronics STM32F05 series Reference Manual

RM0091
23.4.2

I2C2 block diagram

The block diagram of the I
Figure 196. I
2
23.4.3 I

C clock requirements

The I2C kernel is clocked by I2CCLK.
The I2CCLK period t
with:
t : SCL low time and t
LOW
t : when enabled, sum of the delays brought by the analog filter and by the digital filter.
filters
Analog filter delay is maximum 260 ns. Digital filter delay is DNF
The PCLK clock period t
with t
SCL
Caution: When the I2C kernel is clocked by PLCK, PCLK must respect the conditions for t
2
C2 interface is shown in
2
C2 block diagram
PCLK
must respect the following conditions:
I2CCLK
t
I2CCLK
: SCL high time
HIGH
must respect the following condition:
PCLK
: SCL period
Doc ID 018940 Rev 1
Figure
Data control
Digital
Shift register
noise
filter
Clock control
Master clock
Digital
generation
noise
Slave clock
filter
stretching
Registers
APB bus
< (t - t ) / 4 and t
LOW filters
t < 4/3 t
PCLK SCL
Inter-integrated circuit (I
195.
Analog
noise
GPIO
filter
logic
Analog
noise
GPIO
filter
logic
< t
I2CCLK HIGH
.
x t
I2CCLK
2
C) interface
I2C2_SDA
I2C2_SCL
MS19874V1
.
I2CCLK
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