Adc Channel Selection Register (Adc_Chselr); Adc Data Register (Adc_Dr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
Bit 11:0 LT[11:0]: Analog watchdog lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to
AWD) on page 187
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
12.12.8

ADC channel selection register (ADC_CHSELR)

Address offset: 0x28
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
CHSEL CHSEL CHSEL CHSEL
15 14 13
rw rw rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:0 CHSELx: Channel-x selection
These bits are written by software and define which channels are part of the sequence of channels to
be converted.
0: Input Channel-x is not selected for conversion
1: Input Channel-x is selected for conversion
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
12.12.9

ADC data register (ADC_DR)

Address offset: 0x40
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
r r r
Bits 31:16 Reserved, must be kept at reset value.
Section 12.8: Analog window watchdog (AWDEN, AWDSGL, AWDCH, AWD_HTR/LTR,
28 27 26 25
Res. Res. Res.
12 11 10 9
CHSEL CHSEL CHSEL
12 11 10 9
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
r r r r
Doc ID 018940 Rev 1
24 23 22 21
Res. Res. Res. Res.
8 7 6
CHSEL CHSEL CHSEL CHSEL
8 7 6
rw rw rw rw
24 23 22 21
Res. Res. Res. Res.
8 7 6
DATA[15:0]
r r r
Analog-to-digital converter (ADC)
20 19 18
Res. Res. Res.
5 4 3 2
CHSEL CHSEL CHSEL
5 4 3 2
rw rw rw
20 19 18
Res. Res. Res.
5 4 3 2
r r r r
17 16
CHSEL CHSEL
17 16
rw rw
1 0
CHSEL CHSEL
1 0
rw rw
17 16
Res. Res.
1 0
r r
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