STMicroelectronics STM32F05 series Reference Manual page 627

RM0091
Bit 11 RTOF: Receiver timeout
Note: 1. If a time equal to the value programmed in RTOR register separates 2 characters,
Bit 10 CTS: CTS flag
Note: If the hardware flow control feature is not supported, this bit is reserved and forced by
Bit 9 CTSIF: CTS interrupt flag
Note: If the hardware flow control feature is not supported, this bit is reserved and forced by
Bit 8 LBDF: LIN break detection flag
Note: If the USART does not support LIN mode, this bit is reserved and forced by hardware
Bit 7 TXE: Transmit data register empty
Note: This bit is used during single buffer transmission.
Universal synchronous asynchronous receiver transmitter (USART)
This bit is set by hardware when the timeout value, programmed in the RTOR register has
lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in
the USART_ICR register.
An interrupt is generated if RTOIE=1 in the USART_CR2 register.
In Smartcard mode, the timeout corresponds to the CWT or BWT timings.
0: Timeout value not reached
1: Timeout value reached without any data reception
RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8,
depending on the oversampling method), RTOF flag is set.
2. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout
has already elapsed when RE is set, then RTOF will be set.
3. If the USART does not support the Receiver timeout feature, this bit is reserved and
forced by hardware to '0'.
This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin.
0: nCTS line set
1: nCTS line reset
hardware to '0'.
This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared
by software, by writing 1 to the CTSCF bit in the USART_ICR register.
An interrupt is generated if CTSIE=1 in the USART_CR3 register.
0: No change occurred on the nCTS status line
1: A change occurred on the nCTS status line
hardware to '0'.
This bit is set by hardware when the LIN break is detected. It is cleared by software, by
writing 1 to the LBDCF in the USART_ICR.
An interrupt is generated if LBDIE = 1 in the USART_CR2 register.
0: LIN Break not detected
1: LIN break detected
to '0'. Please refer to
This bit is set by hardware when the content of the USART_TDR register has been
transferred into the shift register. It is cleared by a write to the USART_TDR register.
The TXE flag can also be cleared by writing 1 to the TXFRQ in the USART_RQR register, in
order to discard the data (only in Smartcard T=0 mode, in case of transmission failure).
An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register)
Doc ID 018940 Rev 1
Section 25.4: USART implementation on page 573.
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