Tim1 Capture/Compare Register 2 (Tim1_Ccr2); Tim1 Capture/Compare Register 3 (Tim1_Ccr3) - STMicroelectronics STM32F05 series Reference Manual

RM0091
15.4.15

TIM1 capture/compare register 2 (TIM1_CCR2)

Address offset: 0x38
Reset value: 0x0000
15 14 13
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Bits 15:0 CCR2[15:0]: Capture/Compare 2 value
15.4.16

TIM1 capture/compare register 3 (TIM1_CCR3)

Address offset: 0x3C
Reset value: 0x0000
15 14 13
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Bits 15:0 CCR3[15:0]: Capture/Compare value
If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register
(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC3 output.
If channel CC3 is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3).
12 11 10 9
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If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).
12 11 10 9
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Doc ID 018940 Rev 1
8 7 6 5
CCR2[15:0]
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8 7 6 5
CCR3[15:0]
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Advanced-control timers (TIM1)
4 3 2
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4 3 2
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1 0
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1 0
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