Timings; Stopping An Ongoing Conversion (Adstp); Figure 25. Analog To Digital Conversion Time - STMicroelectronics STM32F05 series Reference Manual

RM0091
12.4.10

Timings

The elapsed time between the start of a conversion and the end of conversion is the sum of
the configured sampling time plus the successive approximation time depending on data
resolution:
t
ADC
t
ADC

Figure 25. Analog to digital conversion time

ADC state
RDY
Analog channel
Internal S/H
set
by SW
ADSTART
EOSMP
EOC
ADC_DR
(1) t
(2) t
12.4.11

Stopping an ongoing conversion (ADSTP)

The software can decide to stop any ongoing conversions by setting ADSTP=1 in the
ADC_CR register.
This will reset the ADC operation and the ADC will be idle, ready for a new operation.
When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is
discarded (ADC_DR register is not updated with the current conversion).
The scan sequence is also aborted and reset (meaning that restarting the ADC would re-
start a new sequence)
Once this procedure is complete, the ADSTP and ADSTART bits are both cleared by
hardware and the software must wait until ADSTART=0 before starting new conversions.
= t + t = [ 1.5
SMPL SAR |min
= t + t = 107.1 ns
SMPL SAR
SAMPLING CH(N)
CH(N)
Sample AIN(N)
(1)
t
SMPL
set
by HW
depends on SMP[2:0]
SMPL
depends on RES[2:0]
SAR
Doc ID 018940 Rev 1
+ 12.5 ] x t
|12bit ADC_CLK
+ 892.8 ns = 1 µs
|min |12bit
CONVERTING CH(N)
Hold AIN(N)
(2)
t
SAR
cleared
by SW
DATA N-1
Analog-to-digital converter (ADC)
(for f = 14 MHz)
|min ADC_CLK
SAMPLING CH(N+1)
CH(N+1)
Sample AIN(N+1)
set
by HW
DATA N
cleared
by SW
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