STMicroelectronics STM32F05 series Reference Manual page 515

RM0091
Overrun/underrun error (OVR)
An overrun or underrun error is detected in slave mode when NOSTRETCH=1 and:
●
In reception when a new byte is received and the RXDR register has not been read yet.
The new received byte is lost, and a NACK is automatically sent as a response to the
new byte.
●
In transmission:
–
–
When an overrun or underrun error is detected, the OVR flag is set in the I2Cx_ISR register,
and an interrupt is generated if the ERRIE bit is set in the I2Cx_CR1 register.
Packet Error Checking Error (PECERR)
This section is relevant only when the SMBus feature is supported. Please refer to
Section 23.3: I2C
A PEC error is detected when the received PEC byte does not match with the I2Cx_PECR
register content. A NACK is automatically sent after the wrong PEC reception.
When an PEC error is detected, the PECERR flag is set in the I2Cx_ISR register, and an
interrupt is generated if the ERRIE bit is set in the I2Cx_CR1 register.
Timeout Error (TIMEOUT)
This section is relevant only when the SMBus feature is supported. Please refer to
Section 23.3: I2C
A timeout error occurs for any of these conditions:
●
TIDLE=0 and SCL remained low for the time defined in the TIMEOUTA[11:0] bits: this is
used to detect a SMBus timeout.
●
TIDLE=1 and both SDA and SCL remained high for the time defined in the TIMEOUTA
[11:0] bits: this is used to detect a bus idle condition.
●
Master cumulative clock low extend time reached the time defined in the
TIMEOUTB[11:0] bits (SMBus t
●
Slave cumulative clock low extend time reached the time defined in TIMEOUTB[11:0]
bits (SMBus t
When a timeout violation is detected in master mode, a STOP condition is automatically
sent.
When a timeout violation is detected in slave mode, SDA and SCL lines are automatically
released.
When an timeout error is detected, the TIMEOUT flag is set in the I2Cx_ISR register, and an
interrupt is generated if the ERRIE bit is set in the I2Cx_CR1 register.
Alert (ALERT)
This section is relevant only when the SMBus feature is supported. Please refer to
Section 23.3: I2C
When STOPF=1 and the first data byte should be sent. The content of the
I2Cx_TXDR register is sent if TXE=0, 0xFF if not.
When a new byte should be sent and the I2Cx_TXDR register has not been
written yet, 0xFF is sent.
implementation.
implementation.
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LOW:SEXT
implementation.
Doc ID 018940 Rev 1
Inter-integrated circuit (I
parameter)
LOW:MEXT
2
C) interface
515/742