Tim15 Capture/Compare Mode Register 1 (Tim15_Ccmr1) - STMicroelectronics STM32F05 series Reference Manual

RM0091
Bit 5 COMG: Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels that have a complementary output.
Bits 4:3 Reserved, always read as 0.
Bit 2 CC2G: Capture/Compare 2 generation
Refer to CC1G description
Bit 1 CC1G: Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).
18.5.7

TIM15 capture/compare mode register 1 (TIM15_CCMR1)

Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.
15 14 13
Res. OC2M[2:0]
IC2F[3:0]
rw rw rw
12 11 10 9
OC2 OC2
PE FE
CC2S[1:0]
IC2PSC[1:0]
rw rw rw rw
Doc ID 018940 Rev 1
General-purpose timers (TIM15/16/17)
8 7 6 5
Res. OC1M[2:0]
IC1F[3:0]
rw rw rw rw
4 3 2 1
OC1 OC1
PE FE
CC1S[1:0]
IC1PSC[1:0]
rw rw rw rw
0
rw
409/742