Tim2 And Tim3 Status Register (Tim2_Sr And Tim3_Sr) - STMicroelectronics STM32F05 series Reference Manual

General-purpose timers (TIM2 and TIM3)
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
Bit 0 UIE: Update interrupt enable
16.4.5

TIM2 and TIM3 status register (TIM2_SR and TIM3_SR)

Address offset: 0x10
Reset value: 0x0000
15 14 13
Res. Res. Res. CC4OF CC3OF CC2OF CC1OF
rc_w0
Bit 15:13 Reserved, always read as 0.
Bit 12 CC4OF: Capture/Compare 4 overcapture flag
Refer to CC1OF description
Bit 11 CC3OF: Capture/Compare 3 overcapture flag
Refer to CC1OF description
Bit 10 CC2OF: Capture/compare 2 overcapture flag
Refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to '0.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:7 Reserved, always read as 0.
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode. It is set when the counter
starts or stops when gated mode is selected. It is cleared by software.
0: No trigger event occurred
1: Trigger interrupt pending
Bit 5 Reserved, always read as 0.
Bit 4 CC4IF: Capture/Compare 4 interrupt flag
Refer to CC1IF description
Bit 3 CC3IF: Capture/Compare 3 interrupt flag
Refer to CC1IF description
Bit 2 CC2IF: Capture/Compare 2 interrupt flag
Refer to CC1IF description
336/742
0: CC2 interrupt disabled
1: CC2 interrupt enabled
0: CC1 interrupt disabled
1: CC1 interrupt enabled
0: Update interrupt disabled
1: Update interrupt enabled
12 11 10 9
rc_w0 rc_w0 rc_w0
Doc ID 018940 Rev 1
8 7 6 5
Res. Res. TIF Res.
rc_w0
4 3 2
CC4IF CC3IF CC2IF CC1IF
rc_w0 rc_w0 rc_w0 rc_w0
RM0091
1 0
UIF
rc_w0