Figure 92. Counter Timing Diagram With Prescaler Division Change From 1 To 2 - STMicroelectronics STM32F05 series Reference Manual

General-purpose timers (TIM2 and TIM3)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update
event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC
register). It can be changed on the fly as this control register is buffered. The new prescaler
ratio is taken into account at the next update event.
Figure 92
ratio is changed on the fly:

Figure 92. Counter timing diagram with prescaler division change from 1 to 2

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and Figure 93 give some examples of the counter behavior when the prescaler
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Update event (UEV)
Prescaler control register
Write a new value in TIMx_PSC
Prescaler buffer
Prescaler counter
Doc ID 018940 Rev 1
F7 F8 F9 FA FB FC 00
0
0
0 1
0
01 02 03
1
1
0 1 0 1 0 1
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