Figure 274. Lsb Justified 16-Bit Or 32-Bit Full-Accuracy With Cpol = 0; Figure 275. Lsb Justified 24-Bit Frame Length With Cpol = 0; Figure 276. Operations Required To Transmit 0X3478Ae - STMicroelectronics STM32F05 series Reference Manual

Serial peripheral interface / inter-IC sound (SPI/I2S)
LSB justified standard
This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit
full-accuracy frame formats).

Figure 274. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0

Figure 275. LSB justified 24-bit frame length with CPOL = 0

●
In transmission mode:
If data 0x3478AE have to be transmitted, two write operations to the SPIx_DR register
are required by software or by DMA. The operations are shown below.

Figure 276. Operations required to transmit 0x3478AE

●
In reception mode:
If data 0x3478AE are received, two successive read operations from the SPIx_DR
register are required on each RXNE event.
658/742
CK
WS
Transmission
SD
MSB
CK
WS
8-bit data
SD
0 forced
First write to Data register
conditioned by TXE=1
0xXX34
Only the 8 LSB of the
half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs.
Doc ID 018940 Rev 1
Reception
16- or 32-bit data
LSB
Channel left
Transmission
24-bit remaining
MSB
Channel left 32-bit
Second write to Data register
conditioned by TXE=1
MSB
Channel right
MS30103V1
Reception
LSB
Channel right
MS30104V1
0x78AE
MS19596V1
RM0091