STMicroelectronics STM32F05 series Reference Manual page 480

Inter-integrated circuit (I
Slave clock stretching (NOSTRETCH = 0)
In default mode, the I2C slave stretches the SCL clock in the following situations:
●
When the ADDR flag is set: the received address matches with one of the enabled
slave addresses. This stretch is released when the ADDR flag is cleared by software
setting the ADDRCF bit.
●
In transmission, if the previous data transmission is completed and no new data is
written in I2Cx_TXDR register, or if the first data byte is not written when the ADDR flag
is cleared (TXE=1). This stretch is released when the data is written to the I2Cx_TXDR
register.
●
In reception when the I2Cx_RXDR register is not read yet and a new data reception is
completed. This stretch is released when I2Cx_RXDR is read.
●
When TCR = 1 in Slave Byte Control mode, reload mode (SBC=1 and RELOAD=1),
meaning that the last data byte has been transferred. This stretch is released when
then TCR is cleared by writing a non-zero value in the NBYTES[7:0] field.
Slave without clock stretching (NOSTRETCH = 1)
When NOSTRETCH = 1 in the I2Cx_CR1 register, the I2C slave does not stretch the SCL
signal.
●
The SCL clock is not stretched while the ADDR flag is set.
● In transmission, the data must be written in the I2Cx_TXDR register before the first
SCL pulse corresponding to its transfer occurs. If not, an underrun occurs, the OVR flag
is set in the I2Cx_ISR register and an interrupt is generated if the ERRIE bit is set in the
I2Cx_CR1 register. The OVR flag is also set when the first data transmission starts and
the STOPF bit is still set (has not been cleared). Therefore, if you clear the STOPF flag
of the previous transfer only after writing the first data to be transmitted in the next
transfer, you ensure that the OVR status is provided, even for the first data to be
transmitted.
●
In reception, the data must be read from the I2Cx_RXDR register before the 9th SCL
pulse (ACK pulse) of the next data byte occurs. If not an overrun occurs, the OVR flag
is set in the I2Cx_ISR register and an interrupt is generated if the ERRIE bit is set in the
I2Cx_CR1 register.
Slave Byte Control Mode
In order to allow byte ACK control in slave reception mode, Slave Byte Control mode must
be enabled by setting the SBC bit in the I2Cx_CR1 register. This is required to be compliant
with SMBus standards.
Reload mode must be selected in order to allow byte ACK control in slave reception mode
(RELOAD=1). To get control of each byte, NBYTES must be initialized to 0x1 in the ADDR
interrupt subroutine, and reloaded to 0x1 after each received byte. When the byte is
received, the TCR bit is set, stretching the SCL signal low between the 8th and 9th SCL
pulses. You can read the data from the I2Cx_RXDR register, and then decide to
acknowledge it or not by configuring the ACK bit in the I2Cx_CR2 register. The SCL stretch
is released by programming NBYTES to a non-zero value: the acknowledge or not-
acknowledge is sent and next byte can be received.
NBYTES can be loaded with a value greater than 0x1, and in this case, the reception flow is
continuous during NBYTES data reception.
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C) interface
Doc ID 018940 Rev 1
RM0091