Software Interrupt Event Register (Exti_Swier); Pending Register (Exti_Pr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
Note: The external wakeup lines are edge triggered. No glitches must be generated on these
lines. If a rising edge on an external interrupt line occurs during a write operation to the
EXTI_FTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.
11.3.5

Software interrupt event register (EXTI_SWIER)

Address offset: 0x10
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
SWIER SWIER SWIER SWIER
15 14 13
rw rw rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 17:0 SWIERx: Software interrupt on line x (x = 17 to 0)
11.3.6

Pending register (EXTI_PR)

Address offset: 0x14
Reset value: undefined
31 30 29
Res. Res. Res. Res.
15 14 13
PR15 PR14 PR13 PR12
rc_w1 rc_w1 rc_w1 rc_w1
28 27 26 25
Res. Res. Res.
12 11 10 9
SWIER SWIER SWIER
12 11 10 9
rw rw rw rw
Bits 19 SWIER19: Software interrupt on line 19
Writing a 1 to this bit when it is at 0 sets PR19 pending bit in EXTI_PR. If the
interrupt is enabled on this line on the EXTI_IMR and EXTI_EMR, an interrupt
request is generated.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a 1
into the bit).
Bits 18 Reserved, must be kept at reset value.
Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in
EXTI_PR. If the interrupt is enabled on this line on the EXTI_IMR and
EXTI_EMR, an interrupt request is generated.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a 1
into the bit).
28 27 26 25
Res. Res. Res.
12 11 10 9
PR11 PR10 PR9
rc_w1 rc_w1 rc_w1
Doc ID 018940 Rev 1
24 23 22 21
Res. Res. Res. Res.
8 7 6
SWIER SWIER SWIER SWIER
8 7 6
rw rw rw rw
24 23 22 21
Res. Res. Res. Res.
8 7 6
PR8 PR7 PR6 PR5
rc_w1 rc_w1 rc_w1 rc_w1
Interrupts and events
20 19 18
SWIER
Res. Res.
19
rw
5 4 3 2
SWIER SWIER SWIER
5 4 3 2
rw rw rw
20 19 18
Res. PR19 Res.
rc_w1
5 4 3 2
PR4 PR3 PR2
rc_w1 rc_w1 rc_w1
17 16
SWIER SWIER
17 16
rw rw
1 0
SWIER SWIER
1 0
rw rw
17 16
PR17 PR16
rc_w1 rc_w1
1 0
PR1 PR0
rc_w1 rc_w1
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