Configuring The Adc; Channel Selection (Chsel, Scandir); Table 31. Latency Between Trigger And Start Of Conversion - STMicroelectronics STM32F05 series Reference Manual

Analog-to-digital converter (ADC)
Table 31.
ADC clock source
Dedicated 14 MHz clock
PCLK divided by 2
PCLK divided by 4
12.4.4

Configuring the ADC

Software must write to the ADCAL and ADEN bits in the ADC_CR register if the ADC is
disabled (ADEN must be 0).
Software must only write to the ADSTART and ADDIS bits in the ADC_CR register only if the
ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and ADDIS
= 0).
For all the other control bits in the ADC_IER, ADC_CFGRi, ADC_SMPR, ADC_TR,
ADC_CHSELR and ADC_CCR registers, software must only write to the configuration
control bits if the ADC is enabled (ADEN = 1) and if there is no conversion ongoing
(ADSTART = 0).
Software must only write to the ADSTP bit in the ADC_CR register if the ADC is enabled
(and possibly converting) and there is no pending request to disable the ADC (ADSTART =
1 and ADDIS = 0)
Note: There is no hardware protection preventing software from making write operations forbidden
by the above rules. If such a forbidden write access occurs, the ADC may enter an
undefined state. To recover correct operation in this case, the ADC must be disabled (clear
ADEN=0 and all the bits in the ADC_CR register).
12.4.5

Channel selection (CHSEL, SCANDIR)

There are up to 19 multiplexed channels:
●
16 analog inputs from GPIO pins (ADC_IN0...ADC_IN15)
●
3 internal analog inputs (Temperature Sensor, Internal Reference Voltage, VBAT
channel)
It is possible to convert a single channel or to automatically scan a sequence of channels.
The sequence of the channels to be converted must be programmed in the ADC_CHSELR
channel selection register: each analog input channel has a dedicated selection bit
(CHSEL0...CHSEL18).
The order in which the channels will be scanned can be configured by programming the bit
SCANDIR bit in the ADC_CFGR1 register:
●
SCANDIR=0: forward scan Channel 0 to Channel 18
● SCANDIR=1: backward scan Channel 18 to Channel 0
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Latency between trigger and start of conversion
JITOFF_D4
bit
0
0
1
Doc ID 018940 Rev 1
JITOFF_D2
Latency between the trigger event
and the start of conversion
bit
0 Latency is not deterministic (jitter)
Latency is deterministic (no jitter)
1
and equal to 2.75 ADC clock cycles
Latency is deterministic (no jitter)
0
and equal to 2.625 ADC clock cycles
RM0091