Figure 50. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded); Figure 51. Counter Timing Diagram, Update Event When Arpe=1 - STMicroelectronics STM32F05 series Reference Manual

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Figure 50. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not

Figure 51. Counter timing diagram, update event when ARPE=1

Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
If the repetition counter is used, the update event (UEV) is generated after downcounting is
repeated for the number of times programmed in the repetition counter register
(TIMx_RCR). Else the update event is generated at each counter underflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
preloaded)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
Write a new value in TIMx_ARR
(TIMx_ARR preloaded)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Auto-reload shadow register
Write a new value in TIMx_ARR
Doc ID 018940 Rev 1
Advanced-control timers (TIM1)
31 32 33 34 35 36 00 01 02 03 04 05 06 07
FF
F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07
F5
F5
36
36
36
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