Spix_I 2 S Prescaler Register (Spix_I2Spr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
Bits 2:1 DATLEN: Data length to be transferred
00: 16-bit data length
01: 24-bit data length
10: 32-bit data length
11: Not allowed
Note: For correct operation, these bits should be configured when the I
Not used in SPI mode
Bit 0 CHLEN: Channel length (number of bits per audio channel)
0: 16-bit wide
1: 32-bit wide
The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to
32-bit by hardware whatever the value filled in.
Note: For correct operation, this bit should be configured when the I
Not used in SPI mode
2
26.7.9 SPIx_I
Address offset: 0x20
Reset value: 0000 0010 (0x0002)
15 14 13
Reserved
Bits 15:10 Reserved: Forced to 0 by hardware
Bit 9 MCKOE: Master clock output enable
0: Master clock output is disabled
1: Master clock output is enabled
Note: This bit should be configured when the I
mode.
Not used in SPI mode.
Bit 8 ODD: Odd factor for the prescaler
0: Real divider value is = I2SDIV *2
1: Real divider value is = (I2SDIV * 2)+1
Refer to Section 26.6.3 on page 660
Note: This bit should be configured when the I
mode.
Not used in SPI mode
Bits 7:0 I2SDIV: I
I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.
Refer to
Note: These bits should be configured when the I
master mode.
Not used in SPI mode.
S prescaler register (SPIx_I2SPR)
12 11 10 9
MCKOE
rw
2
S linear prescaler
Section 26.6.3 on page 660
Doc ID 018940 Rev 1
Serial peripheral interface / inter-IC sound (SPI/I2S)
8 7 6 5
ODD
rw
2
S is disabled. It is used only when the I
2
S is disabled. It is used only when the I
2
S is disabled. It is used only when the I
2
S is disabled.
2
S is disabled.
4 3 2 1
I2SDIV
rw
2
S is in master
2
S is in master
2
S is in
0
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