Window Register (Iwdg_Winr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
21.4.5

Window register (IWDG_WINR)

Address offset: 0x10
Reset value: 0x0000 0FFF (reset by Standby mode)
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value.
Bits11:0 WIN[11:0]: Watchdog counter window value
Note: Reading this register returns the reload value from the V
Note: If several reload, prescaler, or window values are used by the application, it is mandatory to
wait until RVU bit is reset before changing the reload value, to wait until PVU bit is reset
before changing the prescaler value, and to wait until WVU bit is reset before changing the
window value. However, after updating the prescaler and/or the reload/window value it is not
necessary to wait until RVU or PVU or WVU is reset before continuing code execution
except in case of low-power mode entry.
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw
These bits are write access protected see
the window value to be compared to the downcounter.
To prevent a reset, the downcounter must be reloaded when its value is lower than the
window register value and greater than 0x0
The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload
value.
may not be valid if a write operation to this register is ongoing. For this reason the value
read from this register is valid only when the WVU bit in the IWDG_SR register is reset.
Doc ID 018940 Rev 1
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
WIN[11:0]
rw rw rw rw
Section 21.3.3. These bits contain the high limit of
Independent watchdog (IWDG)
20 19 18
Res. Res. Res.
4 3 2
rw rw rw
voltage domain. This value
DD
17 16
Res. Res.
1 0
rw rw
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