Tim14 Interrupt Enable Register (Tim14_Dier); Tim14 Status Register (Tim14_Sr) - STMicroelectronics STM32F05 series Reference Manual

General-purpose timer (TIM14)
17.4.2

TIM14 interrupt enable register (TIM14_DIER)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:2
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
Bit 0 UIE: Update interrupt enable
17.4.3

TIM14 status register (TIM14_SR)

Address offset: 0x10
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bit 15:10 Reserved, must be kept at reset value.
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to '0'.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:2 Reserved, must be kept at reset value.
Bit 1 CC1IF: Capture/compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value. It is cleared by
software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit
goes high on the counter overflow.
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred.
1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected
on IC1 which matches the selected polarity).
366/742
12 11 10 9
Res. Res. Res.
Reserved, must be kept at reset value.
0: CC1 interrupt disabled
1: CC1 interrupt enabled
0: Update interrupt disabled
1: Update interrupt enabled
12 11 10 9
Res. Res. CC1OF
rc_w0
Doc ID 018940 Rev 1
8 7 6 5
Res. Res. Res. Res.
8 7 6 5
Res. Res. Res. Res.
4 3 2 1
Res. Res. Res. CC1IE
rw
4 3 2 1
Res. Res. Res. CC1IF
rc_w0
RM0091
0
UIE
rw
0
UIF
rc_w0