Tsc I/O Channel Control Register (Tsc_Ioccr); Tsc I/O Group Control Status Register (Tsc_Iogcsr) - STMicroelectronics STM32F05 series Reference Manual

Advanced arm-based 32-bit mcus
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Touch sensing controller (TSC)
27.6.8

TSC I/O channel control register (TSC_IOCCR)

Address offset: 0x28
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:0 Gx_IOy: Gx_IOy channel mode
These bits are set and cleared by software to configure the Gx_IOy as a channel I/O.
0: Gx_IOy unused
1: Gx_IOy used as channel
Note: These bits must not be modified when an acquisition is on-going.
27.6.9

TSC I/O group control status register (TSC_IOGCSR)

Address offset: 0x30
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:16 GxS: Analog I/O group x status
Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O
Bits 15:6 Reserved, must be kept at reset value.
696/742
28
27
26
25
Res.
Res.
Res.
12
11
10
9
rw
rw
rw
rw
During the acquisition phase and even if the TSC peripheral alternate function is not
enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch
is automatically controlled by the touch sensing controller.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
These bits are set by hardware when the acquisition on the corresponding enabled analog
I/O group x is complete. They are cleared by hardware when a new acquisition is started.
0: Acquisition on analog I/O group x is on-going or not started
1: Acquisition on analog I/O group x is complete
groups are not set.
Doc ID 018940 Rev 1
24
23
22
21
Res.
G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw
rw
rw
8
7
6
5
rw
rw
rw
rw
24
23
22
21
Res.
Res.
Res.
G6S
r
8
7
6
5
Res.
Res.
Res.
G6E
rw
20
19
18
17
rw
rw
rw
rw
4
3
2
1
rw
rw
rw
rw
20
19
18
17
G5S
G4S
G3S
G2S
r
r
r
r
4
3
2
1
G5E
G4E
G3E
G2E
rw
rw
rw
rw
RM0091
16
rw
0
rw
16
G1S
r
0
G1E
rw

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