STMicroelectronics STM32F05 series Reference Manual page 195

RM0091
Bit 4 ADSTP: ADC stop conversion command
This bit is set by software to stop and discard an ongoing conversion (ADSTP Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept
a new start conversion command.
0: No ADC stop conversion command ongoing
1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.
Note: Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 (ADC is enabled and
may be converting and there is no pending request to disable the ADC)
Bit 3 Reserved, must be kept at reset value.
Bit 2 ADSTART: ADC start conversion command
This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a
conversion either starts immediately (software trigger configuration) or once a hardware trigger event
occurs (hardware trigger configuration).
It is cleared by hardware:
– In single conversion mode when software trigger is selected (EXTSEL=0x0): at the assertion of the
End of Conversion Sequence (EOSEQ) flag.
– In all cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is
cleared by hardware.
0: No ADC conversion is ongoing.
1: Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.
Note: Software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and
there is no pending request to disable the ADC)
Bit 1 ADDIS: ADC disable command
This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF
state).
It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at
this time).
0: No ADDIS command ongoing
1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
Note: Software is allowed to set ADDIS only when ADEN=1 and ADSTART=0 (which ensures that no
conversion is ongoing)
Bit 0 ADEN: ADC enable command
This bit is set by software to enable the ADC. The ADC will be effectively ready to operate once the
ADRDY flag has been set.
It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.
0: ADC is disabled (OFF state)
1: Write 1 to enable the ADC.
Note: Software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0,
ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0)
Doc ID 018940 Rev 1
Analog-to-digital converter (ADC)
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