How To Program The Watchdog Timeout; Figure 194. Window Watchdog Timing Diagram - STMicroelectronics STM32F05 series Reference Manual

RM0091
case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to
avoid the WWDG reset, then trigger the required actions.
The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register.
Note: When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task,
the WWDG reset will eventually be generated.
22.4

How to program the watchdog timeout

You can use the formula in
Warning:

Figure 194. Window watchdog timing diagram

The formula to calculate the timeout value is given by:
where:
t
WWDG
t
PCLK
Refer to the datasheet for the minimum and maximum values of the T
Figure 194
When writing to the WWDG_CR register, always write 1 in the
T6 bit to avoid generating an immediate reset.
T[6:0] CNT downcounter
W[6:0]
0x3F
Refresh not allowed
T6 bit
RESET
t t
=
WWDG PCLK1
: WWDG timeout
: APB1 clock period measured in ms
Doc ID 018940 Rev 1
System window watchdog (WWDG)
to calculate the WWDG timeout.
Refresh allowed
WDGTB
× × ×
4096 2
Time
( [ ] ) ( )
t
5:0 + 1 ms
WWDG.
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