STMicroelectronics STM32F05 series Reference Manual page 530

Inter-integrated circuit (I
Bit 2 RXNE: Receive data register not empty (receivers)
Note: This bit is cleared by hardware when PE=0 or SWRST is set.
Bit 1 TXIS: Transmit interrupt status (transmitters)
Note: This bit is cleared by hardware when PE=0 or SWRST is set.
Bit 0 TXE: Transmit data register empty (transmitters)
Note: This bit is set by hardware when PE=0 or SWRST is set.
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C) interface
This bit is set by hardware when the received data is copied into the I2Cx_RXDR register,
and is ready to be read. It is cleared when I2Cx_RXDR is read.
This bit is set by hardware when the I2Cx_TXDR register is empty and the data to be
transmitted must be written in the I2Cx_TXDR register. It is cleared when the next data to be
sent is written in the I2Cx_TXDR register.
This bit can be written to '1' by software when NOSTRETCH=1 only, in order to generate a
TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1).
This bit is set by hardware when the I2Cx_TXDR register is empty. It is cleared when the
next data to be sent is written in the I2Cx_TXDR register.
This bit can be written to '1' by software in order to flush the transmit data register
I2Cx_TXDR.
Doc ID 018940 Rev 1
RM0091