Tim15 Dma/Interrupt Enable Register (Tim15_Dier) - STMicroelectronics STM32F05 series Reference Manual

General-purpose timers (TIM15/16/17)
18.5.4

TIM15 DMA/interrupt enable register (TIM15_DIER)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
Res. TDE Res. Res.
rw
Bit 15 Reserved, always read as 0.
Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled
1: Trigger DMA request enabled
Bits 13:11 Reserved, always read as 0.
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled
1: CC2 DMA request enabled
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE: Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Bit 5 COMIE: COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bits 4:3 Reserved, always read as 0.
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled
406/742
12 11 10 9
Res. CC2DE CC1DE
rw rw
Doc ID 018940 Rev 1
8 7 6 5
UDE BIE TIE COMIE
rw rw rw rw
4 3 2 1
Res. Res. CC2IE CC1IE
rw rw
RM0091
0
UIE
rw