STMicroelectronics STM32F05 series Reference Manual page 644

Serial peripheral interface / inter-IC sound (SPI/I2S)
In receive-only modes, half duplex (BIDIMODE=1, BIDIOE=0) or simplex (BIDIMODE=0,
RXONLY=1) the master starts the sequence immediately when both SPI is enabled and
receive-only mode is activated. The clock signal is provided by the master and it does not
stop until either SPI or receive-only mode is disabled by the master. The master receives
data frames continuously up to this moment.
The slave can not control or delay sequences or data frame starts. For this reason a slave
must always be ready and always have the transfer data prepared (stored at TXFIFO) before
transmission starts. The master has to provide the slave enough time between each
sequence to allow the preparation of data. If possible, the number of data frames in
sequences should be limited in order to enable automatic data handling on the slave side
(by using DMA or FIFOs). The master must provide additional time for the slave to handle
data frame content.
Each sequence must be encased by the NSS pulse in parallel with the multislave system to
select just one of the slaves for communication. In a single slave system it is not necessary
to control the slave with NSS, but it is often better to provide the pulse here too, to
synchronize the slave with the beginning of each data sequence. NSS can be managed by
both software and hardware (see
When the BSY bit is set it signifies an ongoing transaction. This, and the FTLVL[1:0] bits,
can be used to check if the transaction is completed. This is necessary before the system
enters Halt mode, as ongoing transactions can be corrupted by a premature entry. The other
reason to test the BSY bit is to manage the end of the NSS signal by software. When the
RXNE flag is raised, it means the end of an ongoing transaction. The last bit is just sampled
and the complete data frame is stored in the RXFIFO.
The master can finish any transaction when it stops providing data for transmission. In this
case, the clock stops after the last data transaction. Special care must be taken in packing
mode when an odd number of data frames is transmitted to prevent dummy byte
transmission (refer to
the only way to stop the clock is to disable either the SPI or the receive-only mode. The
disable must be performed in a specific time window when the last data frame is ongoing, in
order to receive a complete number of expected data frames and prevent any additional
dummy data reading. The disable control must occur just between the sampling time of the
first bit of the last received frame and first bit of next (unwanted dummy) data frame.
Procedure for disabling the SPI
The master must not disable the SPI (by clearing the SPE bit) while a frame transmission is
ongoing, or any data is stored in TXFIFO. If this happens, the clock signal continues until the
peripheral is enabled again and transmission can be fully completed. Data received but still
not read remains stored in RXFIFO when the SPI is disabled, and must be processed the
next time the SPI is enabled, before starting a new sequence. To prevent this, ensure that
RXFIFO is empty when disabling the SPI. This can be done by using the correct disabling
procedure, or by initializing all the SPI registers with a software reset via the control of a
specific register dedicated to peripheral reset (see the SPIiRST bits in the RCC_APBiRSTR
registers).
The correct disable procedure is (except when receive only mode is used):
1. Wait until FTLVL[1:0] = 00 (no more data to transmit)
2. Wait until BSY=0 (the last data frame is processed)
3. Read data until FRLVL[1:0] = 00 (read all the received data)
4. Disable the SPI (SPE=0).
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Section 26.3.4: Slave select (NSS) pin
Section 26.4.2: TI mode). When the master is in receive-only mode,
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RM0091
management).