Stop Mode; Table 14. Sleep-Now; Table 15. Sleep-On-Exit - STMicroelectronics STM32F05 series Reference Manual

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Table 14.
Sleep-now mode
Mode entry
Mode exit
Wakeup latency
Table 15.
Sleep-on-exit
Mode entry
Mode exit
Wakeup latency
6.3.4

Stop mode

The Stop mode is based on the Cortex-M0 deepsleep mode combined with peripheral clock
gating. The voltage regulator can be configured either in normal or low-power mode. In Stop
mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE oscillators
are disabled. SRAM and register contents are preserved.
In the Stop mode, all I/O pins keep the same state as in the Run mode.
Entering Stop mode
Refer to
To further reduce power consumption in Stop mode, the internal voltage regulator can be
put in low-power mode. This is configured by the LPDS bit of the
(PWR_CR).
If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB
access is finished.
In Stop mode, the following features can be selected by programming individual control bits:
●
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 21.3: IWDG functional description
(IWDG).
Sleep-now
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 0
Refer to the Cortex-M0 System Control register.
If WFI was used for entry:
Interrupt: Refer to
If WFE was used for entry
Wakeup event: Refer to
None
Sleep-on-exit
WFI (wait for interrupt) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex-M0 System Control register.
Interrupt: Refer to
None
Table 16 for details on how to enter the Stop mode.
Doc ID 018940 Rev 1
Description
Table 27: Vector table
Section 11.2.3: Wakeup event management
Description
Table 27: Vector table.
in Section 21: Independent watchdog
Power control (PWR)
Power control register
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