Dma Functional Description; Dma Transactions; Figure 18. Dma Block Diagram - STMicroelectronics STM32F05 series Reference Manual

RM0091
The block diagram is shown in the following figure.

Figure 18. DMA block diagram

Cortex-M0
DMA
Arbiter
AHB Slave
10.3

DMA functional description

The DMA controller performs direct memory transfer by sharing the system bus with the
Cortex-M0 core. The DMA request may stop the CPU access to the system bus for some
bus cycles, when the CPU and DMA are targeting the same destination (memory or
peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half
of the system bus bandwidth (both to memory and peripheral) for the CPU.
10.3.1

DMA transactions

After an event, the peripheral sends a request signal to the DMA Controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA
Controller. The peripheral releases its request as soon as it gets the Acknowledge from the
DMA Controller. Once the request is deasserted by the peripheral, the DMA Controller
release the Acknowledge. If there are more requests, the peripheral can initiate the next
transaction.
In summary, each DMA transfer consists of three operations:
●
The loading of data from the peripheral data register or a location in memory
addressed through an internal current peripheral/memory address register. The start
System
Ch.1
DMA
Ch.2
Ch.7
Doc ID 018940 Rev 1
Direct memory access controller (DMA)
FLITF
Reset & clock
CRC
control (RCC)
Flash
SRAM
Bridge
APB
DAC SPI3/I2S
ADC1
PWR SPI2/I2S
ADC2
ADC3
BKP
USART1
bxCAN WWDG
SPI1
USB
TIM1
I2C2
TIM8
I2C1
GPIOA
UART5
GPIOB
UART4
EXTI
USAR T3
AFIO
USAR T2
MS19218V1
IWDG
RTC
TIM7
TIM6
TIM5
TIM4
TIM3
TIM2
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