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STMicroelectronics STM32WLEx Reference Manual

STMicroelectronics STM32WLEx Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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RM0461

Reference manual

®

STM32WLEx advanced Arm

-based 32-bit MCUs

with sub-GHz radio solution

Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32WLEx microcontrollers memory and peripherals.

STM32WLEx microcontrollers with integrated sub-GHZ radio operating in the

150 - 960 MHz ISM band, belong to a family of microcontrollers with different memory sizes,

packages and peripherals.

For ordering information, mechanical and electrical device characteristics, refer to the

corresponding datasheets.

®

®

®

For information on the Arm

Cortex

-M4 core, refer to the corresponding Arm

Technical

Reference Manuals available on http://infocenter.arm.com.

STM32WLEx microcontrollers include ST state-of-the-art patented technology.

Related documents

• STM32WLE5xx STM32WLE4xx datasheet (DS13105)

For information on the device errata with respect to the datasheet and reference manual,

refer to the STM32WLE5xx STM32WLE4xx errata sheet (ES0506).

April 2022

RM0461 Rev 5

1/1306

www.st.com

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Summary of Contents for STMicroelectronics STM32WLEx

Page 1 Introduction This reference manual targets application developers. It provides complete information on how to use the STM32WLEx microcontrollers memory and peripherals. STM32WLEx microcontrollers with integrated sub-GHZ radio operating in the 150 - 960 MHz ISM band, belong to a family of microcontrollers with different memory sizes, packages and peripherals.
Page 2: Table Of Contents
Contents RM0461 Contents Documentation conventions ....... . . 55 General information ......... 55 List of abbreviations for registers .
Page 3 RM0461 Contents 3.4.2 Option bytes programming ........83 Flash memory protection .
Page 4: Sub-Ghz Radio Generic Synchronization Word Control Register
Contents RM0461 4.3.5 RF-PLL ..........113 4.3.6 Intermediate frequencies .
Page 5: Sub-Ghz Radio Generic Synchronization Word Control Register
RM0461 Contents 4.9.1 Basic sequence for LoRa, (G)MSK and (G)FSK transmit operation . . 159 4.9.2 Basic sequence for LoRa and (G)FSK receive operation ..160 4.9.3 Basic sequence for BPSK transmit operation ....161 4.10 Sub-GHz radio registers .
Page 6: Sub-Ghz Radio Generic Synchronization Word Control Register
Contents RM0461 4.10.22 Sub-GHz radio generic synchronization word control register 3 (SUBGHZ_GSYNCR3) ........168 4.10.23 Sub-GHz radio generic synchronization word control register 2 (SUBGHZ_GSYNCR2) .
Page 7 RM0461 Contents 4.10.49 Sub-GHz radio disable mixer register (REG_ANA_MIXER) ..175 4.10.50 Sub-GHz radio PA over current protection register (SUBGHZ_PAOCPR) ........175 4.10.51 Sub-GHz radio RTC control register (SUBGHZ_RTCCTLR) .
Page 8 Contents RM0461 5.4.7 Stop 0 mode ..........203 5.4.8 Stop 1 mode .
Page 9 RM0461 Contents 6.2.3 MSI clock ..........238 6.2.4 PLL .
Page 10 Contents RM0461 6.4.17 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) ..272 6.4.18 RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . 273 6.4.19 RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . 274 6.4.20 RCC APB2 peripheral clock enable register (RCC_APB2ENR) .
Page 11 RM0461 Contents 7.4.1 HSEM register semaphore x (HSEM_Rx) ..... . 303 7.4.2 HSEM read lock register semaphore x (HSEM_RLRx) ... . 304 7.4.3 HSEM interrupt enable register (HSEM_IER) .
Page 12 Contents RM0461 8.4.8 GPIOx configuration lock register (GPIOx_LCKR) (x = A to B) ..322 8.4.9 GPIOx alternate function low register (GPIOx_AFRL) (x = A to B) . . . 323 8.4.10 GPIOx alternate function high register (GPIOx_AFRH) (x = A to B) . . 323 8.4.11 GPIOx bit reset register (GPIOx_BRR) (x = A to B) .
Page 13 RM0461 Contents 9.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) ........344 9.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) .
Page 14 Contents RM0461 11.3 DMA implementation ........360 11.3.1 DMA1 and DMA2 .
Page 15 RM0461 Contents 12.6.1 DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR) ........393 12.6.2 DMAMUX request line multiplexer interrupt channel status register (DMAMUX_CSR) .
Page 16 Contents RM0461 14.6.11 EXTI interrupt mask register (EXTI_IMR2) ..... 418 14.6.12 EXTI register map ........418 Cyclic redundancy check calculation unit (CRC) .
Page 17 RM0461 Contents 16.4 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . 442 16.4.1 Discontinuous mode (DISCEN) ......443 16.4.2 Programmable resolution (RES) - Fast conversion mode .
Page 18 Contents RM0461 16.12.7 ADC watchdog threshold register (ADC_AWD1TR) ....476 16.12.8 ADC watchdog threshold register (ADC_AWD2TR) ....477 16.12.9 ADC channel selection register (ADC_CHSELR) .
Page 19 RM0461 Contents 17.7.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) ........504 17.7.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) .
Page 20 Contents RM0461 19.3.6 Hysteresis ..........520 19.3.7 Comparator output blanking function .
Page 21 RM0461 Contents 21.1 Introduction ..........544 21.2 AES main features .
Page 22 Contents RM0461 21.7.13 AES key register 4 (AES_KEYR4) ......588 21.7.14 AES key register 5 (AES_KEYR5) ......588 21.7.15 AES key register 6 (AES_KEYR6) .
Page 23 RM0461 Contents 22.5.1 Supported elliptic curves ........610 22.5.2 Computation times .
Page 24 Contents RM0461 23.3.24 Timer input XOR function ........670 23.3.25 Interfacing with Hall sensors .
Page 25 RM0461 Contents 23.4.22 TIM1 DMA address for full transfer (TIM1_DMAR) ......... . . 708 23.4.23 TIM1 option register 1 (TIM1_OR1) .
Page 26 Contents RM0461 24.3.21 Debug mode ..........762 24.4 TIM2 registers .
Page 27 RM0461 Contents 25.3.5 Capture/compare channels ....... . . 801 25.3.6 Input capture mode .
Page 28 Contents RM0461 25.4.20 TIM17 option register 1 (TIM17_OR1) ......837 25.4.21 TIM17 alternate function register 1 (TIM17_AF1) ....838 25.4.22 TIM17 input selection register (TIM17_TISEL) .
Page 29 RM0461 Contents 26.7.7 LPTIM autoreload register (LPTIM_ARR) ..... . 865 26.7.8 LPTIM counter register (LPTIM_CNT) ......866 26.7.9 LPTIM1 option register (LPTIM1_OR) .
Page 30 Contents RM0461 29.3.6 Debug mode ..........884 29.4 WWDG interrupts .
Page 31 RM0461 Contents 30.6.5 RTC prescaler register (RTC_PRER) ......911 30.6.6 RTC wakeup timer register (RTC_WUTR) ..... . 912 30.6.7 RTC control register (RTC_CR) .
Page 32 Contents RM0461 31.6.6 TAMP status register (TAMP_SR) ......941 31.6.7 TAMP masked interrupt status register (TAMP_MISR) ... . 942 31.6.8 TAMP status clear register (TAMP_SCR) .
Page 33 RM0461 Contents 32.7.4 I2C own address 2 register (I2C_OAR2) ..... . 1005 32.7.5 I2C timing register (I2C_TIMINGR) ......1006 32.7.6 I2C timeout register (I2C_TIMEOUTR) .
Page 34 Contents RM0461 33.5.21 USART low-power management ......1061 33.6 USART in low-power modes ....... . 1064 33.7 USART interrupts .
Page 35 RM0461 Contents 34.4.11 LPUART single-wire Half-duplex communication ....1120 34.4.12 Continuous communication using DMA and LPUART ... . 1120 34.4.13 RS232 Hardware flow control and RS485 Driver Enable .
Page 36 Contents RM0461 35.5.10 SPI status flags ......... 1176 35.5.11 SPI error flags .
Page 37 RM0461 Contents 36.3.4 DBG power domains ........1215 36.3.5 DBG low-power modes .
Page 38 Contents RM0461 36.6.12 DWT CoreSight peripheral identity register 4 (DWT_PIDR4) ..1245 36.6.13 DWT CoreSight peripheral identity register 0 (DWT_PIDR0) ..1245 36.6.14 DWT CoreSight peripheral identity register 1 (DWT_PIDR1) ..1246 36.6.15 DWT CoreSight peripheral identity register 2 (DWT_PIDR2) .
Page 39 RM0461 Contents 36.9.1 ITM stimulus register x (ITM_STIMRx) ..... . . 1266 36.9.2 ITM trace enable register (ITM_TER) ......1267 36.9.3 ITM trace privilege register (ITM_TPR) .
Page 40 Contents RM0461 36.11.1 DBGMCU identity code register (DBGMCU_IDCODER) ..1287 36.11.2 DBGMCU configuration register (DBGMCU_CR) ....1287 36.11.3 DBGMCU APB1 peripheral freeze register 1 (DBGMCU_APB1FZR1) .
Page 41 RM0461 List of tables List of tables Table 1. Device boot mode ............59 Table 2.
Page 42 Table 65. STM32WLEx peripherals interconnect matrix ....... . . 351 Table 66.
Page 43 RM0461 List of tables Table 103. Sample and refresh timings ..........496 Table 104.
Page 44 Table 177. STM32WLEx LPTIM features ........
Page 45 Table 242. LPUART register map and reset values ........1153 Table 243. STM32WLEx SPI and SPI/I2S implementation ....... 1156 Table 244.
Page 46 List of tables RM0461 Table 257. AP register map and reset values......... . 1237 Table 258.
Page 47 RM0461 List of figures List of figures Figure 1. System architecture ............58 Figure 2.
Page 48 List of figures RM0461 Figure 49. ADC connectivity ............436 Figure 50.
Page 49 RM0461 List of figures Figure 101. Message construction in CTR mode......... 560 Figure 102.
Page 50 List of figures RM0461 Figure 153. 3-phase combined PWM signals with multiple trigger pulses per period ... . . 653 Figure 154. Complementary output with dead-time insertion ....... 654 Figure 155.
Page 51 RM0461 List of figures Figure 204. Edge-aligned PWM waveforms (ARR=8) ........743 Figure 205.
Page 52 List of figures RM0461 Figure 252. LPTIM output waveform, Continuous counting mode configuration ....850 Figure 253. Waveform generation ........... . 851 Figure 254.
Page 53 RM0461 List of figures Figure 303. Break detection in LIN mode vs. Framing error detection......1044 Figure 304. USART example of synchronous master transmission......1045 Figure 305.
Page 54 List of figures RM0461 Figure 348. TI mode transfer ............1179 Figure 349.
Page 55: Documentation Conventions
Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of them may not be used in the current document.
Page 56: Glossary
Documentation conventions RM0461 Glossary This section gives a brief definition of acronyms and abbreviations used in this document: • Word: data of 32-bit length. • Half-word: data of 16-bit length. • Byte: data of 8-bit length. • Option bytes: product configuration bits stored in the Flash memory. •...
Page 57: Memory And Bus Architecture
RM0461 Memory and bus architecture Memory and bus architecture The following definition is used in this section: • CPU = Arm Cortex-M4 with MPU and DSP System architecture The main system consists of a 32-bit multilayer AHB bus matrix that interconnects the following masters and slaves: •...
Page 58: S0: Cpu I-Bus
Memory and bus architecture RM0461 This architecture is shown in the figure below. Figure 1. System architecture DMA1 DMA2 Cortex-M4 S0 S1 S2 Flash memory FLASH arbiter SRAM1 SRAM2 AHB1 AHB2 AHB3 when remapped Bus matrix MSv60753V1 2.1.1 S0: CPU I-bus This bus connects the instruction bus of the CPU core to the bus matrix.
Page 59: S4, S5: Dma-Bus
RM0461 Memory and bus architecture 2.1.4 S4, S5: DMA-bus These buses connect the AHB master interface of the DMAs to the bus matrix.The targets of this bus are the internal flash memory, SRAM1, SRAM2 the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the AHB3 peripherals including the APB3 peripherals.
Page 60 Memory and bus architecture RM0461 Table 1. Device boot mode (continued) Boot mode selection CPU aliasing space User Flash boot System Flash boot System Flash boot SRAM1 boot User Flash boot User Flash boot System Flash boot System Flash boot SRAM1 boot User Flash boot Values on BOOT0 and BOOT1 are latched after a reset.
Page 61: Sram Erase
SRAM memory Embedded bootloader The embedded bootloader is located in the system flash memory, programmed by STMicroelectronics during production. It is used to program the flash memory using one of the following device interfaces: • USART1 on pins PA9 and PA10 •...
Page 62: Memory Organization
RM0461 Memory organization 2.4.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.
Page 63: Memory Map And Register Boundary Addresses
RM0461 2.4.2 Memory map and register boundary addresses Figure 2. Memory map 0xFFFF FFFF 0x5801 FFFF APB3 0x5801 0000 internal AHB3 peripherals 0x5800 0000 AHB2 0xE000 0000 0x4800 0000 AHB1 0x4802 0000 APB2 0x4001 0000 APB1 0x4000 0000 0x2000 FFFF SRAM2 0x2000 8000 SRAM1...
Page 64: Table 3. Memory Map And Peripheral Register Boundary Addresses
RM0461 The table below details the boundary addresses of peripherals available in the device. Table 3. Memory map and peripheral register boundary addresses Size Boundary address Peripheral Peripheral register map (bytes) 0x5801 0400 - 0x5801 FFFF Reserved APB3 0x5801 0000 - 0x5801 03FF SUBGHZSPI Section 35.9.10: SPI/I2S register map 0x5800 4400 - 0x5800 FFFF...
Page 65 RM0461 Table 3. Memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4001 4C00 - 0x4001 FFFF Reserved Section 25.4.23: TIM16/TIM17 register 0x4001 4800 - 0x4001 4BFF TIM17 Section 25.4.23: TIM16/TIM17 register 0x4001 4400 - 0x4001 47FF TIM16 0x4001 3C00 - 0x4001 43FF Reserved...
Page 66 RM0461 Table 3. Memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4000 B400 - 0x4000 FFFF Reserved 0x4000 B000 - 0x4000 B3FF TAMP Section 31.6.11: TAMP register map 0x4000 9C00 - 0x4000 AFFF Reserved 0x4000 9800 - 0x4000 9BFF LPTIM3...
Page 67: Cpu Bit Banding
RM0461 Table 3. Memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x1FFF 7800 - 0x1FFF 7FFF Flash user options Section 3.8.14: FLASH register map 0x1FFF 7400 - 0x1FFF 77FF Flash Engi AHB3 0x1FFF 7000 - 0x1FFF 73FF Flash OTP Flash RSS and...
Page 68 RM0461 Example The following example shows how to map bit [2] of the byte located at SRAM1 address 0x2000 0300 to the alias region. The formula is then: 0x2200 6008 = 0x2200 0000 + 0x0300 * 32 + 2 * 4 Writing to address 0x2200 6008 has the same effect as a read-modify-write operation on bit [2] of the byte at SRAM1 address 0x2000 0300.
Page 69: Embedded Flash Memory (Flash)
RM0461 Embedded flash memory (FLASH) Embedded flash memory (FLASH) FLASH introduction The flash memory interface manages the CPU AHB ICode and DCode accesses to the flash memory. It implements the access, the erase and program flash memory operations, and the read and write protection. The flash memory interface accelerates code execution with a system of instruction prefetch and cache lines.
Page 70: Empty Check
This area is reserved and contains the bootloader used to reprogram the flash memory through one of the following interfaces: USART1, USART2, I2C1, I2C2, I2C3, SPI1, SPI2S2. It is programmed by STMicroelectronics when the device is manufactured and protected against spurious write/erase operations. For further details, refer to the application note STM32 microcontroller system memory boot mode (AN2606).
Page 71: Error Code Correction (Ecc)
RM0461 Embedded flash memory (FLASH) defines the main flash memory as target boot area. When this flag is set, the device is considered as empty and the system memory (bootloader) is selected instead of the main flash memory as a boot area, to allow the user to program the flash memory. Therefore, some of the GPIOs are reconfigured from the High-Z state.
Page 72: Adaptive Real-Time Memory Accelerator (Art Accelerator)
Embedded flash memory (FLASH) RM0461 The table below shows the correspondence between wait states and frequency of the flash memory clock. Table 5. Number of wait states according to flash clock (HCLK3) frequency HCLK3 (MHz) Wait states (WS) (access) range 1 range 2 CORE CORE...
Page 73 RM0461 Embedded flash memory (FLASH) performance advantage of the Cortex-M4 with DSP over flash memory technologies, which normally require the processor to wait for the flash memory at higher operating frequencies. To release the processor full performance, the accelerator implements an instruction prefetch queue and branch cache that increases program execution speed from the 64-bit ®...
Page 74: Figure 3. Sequential 16 Bits Instructions Execution
Embedded flash memory (FLASH) RM0461 The figure below shows the execution of sequential 16-bit instructions with and without prefetch when three wait states are needed to access the flash memory. Figure 3. Sequential 16 bits instructions execution WAIT WITHOUT PREFETCH WAIT ins 1 ins 2...
Page 75: Flash Program And Erase Operations
RM0461 Embedded flash memory (FLASH) When the code is not sequential (branch), the instruction may not be present in the currently used instruction line or in the prefetched instruction line. In this case (miss), the penalty in terms of number of cycles is at least equal to the number of wait states. If a loop is present in the current buffer, no new access is performed.
Page 76: Flash Main Memory Erase Sequences
Embedded flash memory (FLASH) RM0461 The contents of the flash memory are not guaranteed if a device reset occurs during a flash memory operation. During a program/erase operation to the flash memory, any attempt to read the flash memory stalls the bus. The read operation proceeds correctly once the program/erase operation is completed.
Page 77: Flash Main Memory Programming Sequences
RM0461 Embedded flash memory (FLASH) To erase a 2-Kbyte page, follow the steps detailed below: Check that no flash memory operation is ongoing by checking BSY in FLASH_SR. Check that flash program and erase operation is allowed by checking PESD in FLASH_SR.
Page 78 Embedded flash memory (FLASH) RM0461 It is only possible to program a double-word (2 x 32-bit data), otherwise: • Any attempt to write a byte (8 bits) or half-word (16 bits) sets SIZERR in FLASH_SR. • Any attempt to write a double-word that is not aligned with a double-word address sets the PGAERR flag in FLASH_SR.
Page 79 RM0461 Embedded flash memory (FLASH) Only the main memory can be programmed in Fast programming mode. The flash main memory programming sequence in Fast programming mode is described below: Perform a mass erase. If not, PGSERR is set. Check that no flash main memory operation is ongoing by checking BSY bit FLASH_SR.
Page 80 Embedded flash memory (FLASH) RM0461 In standard programming or in fast programming: only double-word can be programmed and only 32-bit data can be written. SIZERR is set if a byte or an half-word is written. • PGAERR: alignment programming error PGAERR is set if one of the following conditions occurs: –...
Page 81: Table 8. Errors In Page-Based Row Programming
RM0461 Embedded flash memory (FLASH) • MISSERR: fast programming data miss error In fast programming, all the data must be written successively. MISSERR is set if the previous data programming is finished and the next data to program is not written yet. •...
Page 82: Flash Option Bytes
Embedded flash memory (FLASH) RM0461 Programming errors causing a bus error The error conditions listed below do not generate an error flag but a bus error instead: • AHB write to any page when RDP level 1 and boot is performed from the system flash memory or SRAM1 •...
Page 83: Option Bytes Programming
RM0461 Embedded flash memory (FLASH) Table 9. Option bytes organization Address RDP[7:0] 0x1FFF 7800 PCROP1A_STRT[7:0] 0x1FFF 7808 PCROP1A_END[7:0] 0x1FFF 7810 WRP1A_END[6:0] WRP1A_STRT[6:0] 0x1FFF 7818 WRP1B_END[6:0] WRP1B_STRT[6:0] 0x1FFF 7820 PCROP1B_STRT[7:0] 0x1FFF 7828 PCROP1B_END[7:0] 0x1FFF 7830 0x1FFF 7838 0x1FFF 7FF0 OPTVAL[31:0] 0x1FFF 7FF8 1.
Page 84 Embedded flash memory (FLASH) RM0461 Modify user options The option bytes are programmed differently from a main memory user address. To modify the user options value, follow the procedure below: Clear OPTLOCK option lock bit with the clearing sequence described above Write the desired options value in the options registers.
Page 85: Flash Memory Protection
RM0461 Embedded flash memory (FLASH) If the comparison between the word and its complement fails, a status bit OPTVERR is set. Mismatch values are forced into the option registers as follows: • For USR OPT option, the value of mismatch is all options at ‘1’, except for BOR_LEV that is “000”...
Page 86: Readout Protection (Rdp)
Embedded flash memory (FLASH) RM0461 Apart from the RDP and WRP, the flash memory can also be protected against read and write from third parties (PCROP). The PCROP granularity is 1 Kbyte. 3.5.1 Readout protection (RDP) The readout protection is activated by setting the RDP option byte and performing an option byte programming with OPTSTRT followed by a OBL_LAUNCH, POR or wakeup from Standby or Shutdown mode.
Page 87: Table 12. Rdp Regression From Level 1 To Level 0 And Memory Erase
Note: The debug feature is also disabled under reset. STMicroelectronics is not able to perform analysis on defective parts on which the level 2 protection has been set. Change the readout protection level It is easy to move from level 0 to level 1 by changing the value of the RDP byte to any value (except 0xCC).
Page 88: Table 13. Access Status Versus Protection Level And Execution Modes
Embedded flash memory (FLASH) RM0461 Figure 4. Changing the RDP level RDP ≠ 0xAA and RDP ≠ 0xCC Others options modified Level 1 RDP ≠ 0xAA RDP ≠ 0xCC default Write options including Write options including Write options including RDP = 0xCC RDP ≠...
Page 89: Proprietary Code Readout Protection (Pcrop)
RM0461 Embedded flash memory (FLASH) 3.5.2 Proprietary code readout protection (PCROP) Two parts of the flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU with an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
Page 90: Write Protection (Wrp)
Embedded flash memory (FLASH) RM0461 Table 14: PCROP protection PCROP registers values (x = A or B) PCROP protection area PCROP1x_STRT = PCROP1x_END No PCROP1x, unprotected PCROP1x_STRT > PCROP1x_END No PCROP1x, unprotected PCROP1x_STRT < PCROP1x_END Pages from PCROP1x_STRT to PCROP1x_END are protected Note: It is recommended to align PCROP areas with the page granularity when using PCROP_RDP, or to leave free the rest of the page where PCROP zones starts or ends.
Page 91: Security (Ese)
RM0461 Embedded flash memory (FLASH) Table 15: WRP protection WRPx registers values (x = A or B) WRP protection area WRP1x_STRT = WRP1x_END Page WRP1x is protected WRP1x_STRT > WRP1x_END No WRP, unprotected WRP1x_STRT < WRP1x_END Pages from WRP1x_STRT to WRP1x_END are protected Note: To validate the WRP options, the option bytes must be reloaded through the OBL_LAUNCH bit in FLASH_CR.
Page 92: Flash Interrupts
Embedded flash memory (FLASH) RM0461 FLASH interrupts Table 16. Flash interrupt requests Event flag/interrupt Interrupt enable Interrupt event Event flag clearing method control bit End of operation Write EOP=1 EOPIE Operation error OPERR Write OPERR=1 ERRIE Readout protection error RDERR Write RDERR=1 RDERRIE Write protection error...
Page 93 RM0461 Embedded flash memory (FLASH) Bits 31:17 Reserved, must be kept at reset value. Bit 16 EMPTY: Flash user area empty When read, this bit indicates whether the first location of the user flash is erased or has a programmed value. 0: Read: user flash programmed 1: Read: user flash empty Bit 15 PES: CPU program/erase suspend request...
Page 94: Flash Key Register (Flash_Keyr)
Embedded flash memory (FLASH) RM0461 3.8.2 FLASH key register (FLASH_KEYR) Address offset: 0x008 Reset value: 0x0000 0000 KEY[31:16] KEY[15:0] Bits 31:0 KEY[31:0]: Flash key The following values must be written consecutively to unlock FLASH_CR, thus enabling programming/erasing operations: KEY1: 0x4567 0123 KEY2: 0xCDEF 89AB 3.8.3 FLASH option key register (FLASH_OPTKEYR)
Page 95: Flash Status Register (Flash_Sr)
RM0461 Embedded flash memory (FLASH) 3.8.4 FLASH status register (FLASH_SR) Address offset: 0x010 Reset value: 0x000X 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PESD CFGBSY Res. OPTNV Res. Res. Res. Res. rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1...
Page 96 Embedded flash memory (FLASH) RM0461 Bit 13 OPTNV: User option OPTVAL indication This bit is set and reset by hardware. 0: The OBL user option OPTVAL indicates “valid” (user option program sequence has not terminated completely). 1: The OBL user option OPTVAL indicates “not valid” (OPTVAL check word has been erroneously read).
Page 97: Flash Control Register (Flash_Cr)
RM0461 Embedded flash memory (FLASH) Bit 2 Reserved, must be kept at reset value. Bit 1 OPERR: Operation error This bit is set by hardware when a flash memory operation (program/erase) completes unsuccessfully. This bit is set only if error interrupts are enabled (ERRIE = 1). This bit is cleared by writing 1.
Page 98 Embedded flash memory (FLASH) RM0461 Bit 31 LOCK: FLASH_CR lock This bit can only be set by software. When set, the FLASH_CR register is locked. This bit is cleared by hardware after detecting the unlock sequence. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. Bit 30 OPTLOCK: Options lock This bit can only be set by software.
Page 99: Flash Ecc Register (Flash_Eccr)
RM0461 Embedded flash memory (FLASH) Bits 9:3 PNB[6:0]: page number selection These bits select the 2-Kbyte page to erase. 0x00: page 0 0x01: page 1 0x3F: page 63 Bit 2 MER: mass erase When set, this bit triggers the mass erase (all user pages). Bit 1 PER: page erase 0: page erase disabled 1: page erase enabled...
Page 100: Flash Option Register (Flash_Optr)
Embedded flash memory (FLASH) RM0461 Bit 20 SYSF_ECC: system flash memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system flash memory. Bits 19:17 Reserved, must be kept at reset value. Bits 16:0 ADDR_ECC[16:0]: ECC fail double-word address This bit indicates that double-word address is concerned by the ECC error correction or causes the double ECC error detection.
Page 101 RM0461 Embedded flash memory (FLASH) Bit 26 nSWBOOT0: software BOOT0 selection 0: BOOT0 taken from the option bit nBOOT0 1: BOOT0 taken from PH3/BOOT0 pin Bit 25 SRAM_RST: SRAM1 and SRAM2 erase when system reset 0: SRAM1 and SRAM2 erased when a system reset occurs 1: SRAM1 and SRAM2 not erased when a system reset occurs Note: PKA SRAM is always erased on any system.
Page 102: Flash Pcrop Zone A Start Address Register (Flash_Pcrop1Asr)
Embedded flash memory (FLASH) RM0461 Bit 8 ESE: system security enable flag When read, this bit indicates whether the system security is enabled, meaning user option FSD = 0. Writing 0 to this bit and regressing the RDP from level 1 to level 0 disables the security 0: Security disabled 1: Security enabled...
Page 103: Flash Pcrop Zone A End Address Register (Flash_Pcrop1Aer)
RM0461 Embedded flash memory (FLASH) 3.8.9 FLASH PCROP zone A end address register (FLASH_PCROP1AER) Address offset: 0x028 Reset value: 0xFFFF FF00 Default reset value from ST production is given. Subsequently, 0bX111 1111 1111 1111 1111 1111 XXXX XXXX, the option bits are loaded with user values from flash memory at reset release.
Page 104: Flash Wrp Area A Address Register (Flash_Wrp1Ar)
Embedded flash memory (FLASH) RM0461 3.8.10 FLASH WRP area A address register (FLASH_WRP1AR) Address offset: 0x02C Reset value: 0xFF80 FFFF Default reset value from ST production is given as.0b1111 1111 1XXX XXXX 1111 1111 1XXX XXXX, the option bits are loaded with user values from the flash memory at reset release.
Page 105: Flash Pcrop Zone B Start Address Register (Flash_Pcrop1Bsr)
RM0461 Embedded flash memory (FLASH) Bits 31:23 Reserved, must be kept at reset value. Bits 22:16 WRP1B_END[6:0]: WRP area B end offset WRPB1_END contains the last 2-Kbyte page of the WRP area B. Bits 15:7 Reserved, must be kept at reset value. Bits 6:0 WRP1B_STRT[6:0]: WRP area B start offset WRPB1_END contains the first 2-Kbyte page of the WRP area B.
Page 106 Embedded flash memory (FLASH) RM0461 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PCROP1B_END[7:0] Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PCROP1B_END[7:0]: PCROP1B area end offset Contains the first 1-Kbyte page of the PCROP1B area.
Page 107: Flash Register Map
RM0461 Embedded flash memory (FLASH) 3.8.14 FLASH register map Table 17. Flash interface register map and reset values Offset Register LATENCY FLASH_ACR [2:0] 0x000 Reset value 0x004 Reserved Reserved. FLASH_KEYR KEYR[31:0] 0x008 Reset value FLASH_ OPTKEY[31:0] OPTKEYR 0x00C Reset value FLASH_SR 0x010 Reset value...
Page 108 Embedded flash memory (FLASH) RM0461 Table 17. Flash interface register map and reset values (continued) Offset Register FLASH_ PCROP1B_STRT[7:0] PCROP1BSR 0x034 Reset value FLASH_ PCROP1B_END[7:0] PCROP1BER 0x038 Reset value Refer to Section 2.4 for the register boundary addresses. 108/1306 RM0461 Rev 5...
Page 109: Sub-Ghz Radio (Subghz)
RM0461 Sub-GHz radio (SUBGHZ) Sub-GHz radio (SUBGHZ) Sub-GHz radio introduction The sub-GHz radio is an ultra-low-power sub-GHz radio operating in the 150 - 960 MHz ISM ® band. LoRa and (G)FSK modulation in transmit and receive, and BPSK/(G)MSK in transmit only, allow an optimal trade-off between range, data rate and power ®...
Page 110: Sub-Ghz Radio Functional Description
Sub-GHz radio (SUBGHZ) RM0461 Sub-GHz radio functional description 4.3.1 General description The sub-GHz radio provides an internal processing unit to handle communication with the system CPU. Communication is handled by commands sent over the SPI interface, and a set of interrupts is used to signal events. BUSY information signals operation activity and is used to indicate when the sub-GHz radio commands cannot be received.
Page 111: Transmitter
RM0461 Sub-GHz radio (SUBGHZ) Table 18. Sub-GHz internal input/output signals (continued) Signal name Signal type Description HSERDY Digital output HSE32 clock ready indication SUBGHZSPI Digital in/output Sub-GHz radio SPI interface BUSY Digital output BUSY signal Interrupts Digital output IRQ interrupts 4.3.3 Transmitter The transmit chain comprises the modulated output from the modem, that directly...
Page 112: Receiver
Sub-GHz radio (SUBGHZ) RM0461 The table below gives the maximum transmit output power versus the V supply level. DDPA Table 19. Sub-GHz radio transmit high output power supply (V) Transmit output power (dBm) DDPA + 22 + 20 + 16 Transmitter low output power The transmit low output power up to + 15 dBm, is supported through the RFO_LP pin.
Page 113: Rf-Pll
RM0461 Sub-GHz radio (SUBGHZ) The receiver features automatic I and Q calibration, that improves image rejection. The calibration is done automatically at startup before using the receiver, and can be requested by command (see Image calibration for specific frequency bands for more details).
Page 114: Sub-Ghz Radio Clocks
Sub-GHz radio (SUBGHZ) RM0461 Table 21. LoRa mode intermediate frequencies Setting name Bandwidth [kHz] [kHz] LORA_BW_500 LORA_BW_250 LORA_BW_125 LORA_BW_62 62.5 LORA_BW_41 41.67 LORA_BW_31 31.25 LORA_BW_20 20.83 LORA_BW_15 15.63 LORA_BW_10 10.42 LORA_BW_7 7.81 Sub-GHz radio clocks 4.4.1 Internal oscillators The following sub-GHz radio dedicated internal RC oscillators are available: •...
Page 115: Sub-Ghz Radio Modems
RM0461 Sub-GHz radio (SUBGHZ) The sub-GHz radio, depending on the transmit output power (max + 22 dBm), can heat up the device. The heating depends on the used transmit output power and the device package. Careful PCB design using thermal heat dissipation techniques must be applied to avoid heat transfer to the HSE32 reference clock source.
Page 116: Table 22. Spreading Factor, Chips/Symbol And Lora Snr
Sub-GHz radio (SUBGHZ) RM0461 Spreading factor (SF) The LoRa spread spectrum modulation is performed by representing each data bit of the packet payload by multiple chips of information. The rate at which the spread information is sent, is referred to as the symbol rate (Rs). The ratio between the nominal data rate and the chip rate is the spreading factor (SF).
Page 117: Lora Framing
RM0461 Sub-GHz radio (SUBGHZ) A higher coding rate provides better immunity to interference at the expense of longer transmission time. In normal conditions and factor of 4 / 5 provides the best trade off. In case of strong interference, a higher coding rate may be used. The coding rate and overhead ratio is given in the table below.
Page 118: Figure 8. Lora Packet Frames Format
Sub-GHz radio (SUBGHZ) RM0461 The LoRa packet frames are illustrated in the figure below. Figure 8. LoRa packet frames format Explicit packet frame n preamble symbols n header symbols Preamble Header + CRC Payload CR defined by coding rate CR = 4/8 SF defined by spreading factor Implicit packet frame n preamble symbols...
Page 119: Fsk Modem
RM0461 Sub-GHz radio (SUBGHZ) Implicit header mode In certain operation modes where the payload coding rate and CRC presence are fixed or known in advance, it can be advantageous to reduce transmission time by invoking implicit header mode. In this mode, the header is not present in the packet frame. The payload length, forward error correction coding rate and presence of the payload CRC must be configured on both sides of the sub-GHz radio link.
Page 120: Msk Modem
Sub-GHz radio (SUBGHZ) RM0461 index. An optional Gaussian filter can be used. All modulation parameters are set using Set_ModulationParams() command. The bit rate (or equivalent chip) is referenced to the HSE32 frequency and controlled by the BR parameter, defined as follows: BR = 32 x HSE32 / BitRate where HSE32 = 32 MHz...
Page 121: Figure 9. Generic Packet Frames Format
RM0461 Sub-GHz radio (SUBGHZ) The generic packet frames are illustrated in the figure below. Figure 9. Generic packet frames format Variable length generic packet frame Address Preamble Syncword Length Payload 0 to 1 byte 8 to 65535 bits 0 – 8 bytes 1 to 255 bytes 0 to 2 bytes CRC check...
Page 122: Bpsk Modem
Sub-GHz radio (SUBGHZ) RM0461 Variable length generic packet mode When the packet is of uncertain or variable length, the information on the payload length must be transmitted within the packet. For this, a header with the payload length information is transmitted after the syncword. Fixed length generic packet mode In certain operation modes where the payload length is fixed or known in advance, it may be advantageous to reduce transmission time by invoking fixed length generic packet mode.
Page 123: Bpsk Framing
RM0461 Sub-GHz radio (SUBGHZ) 4.5.7 BPSK framing The BPSK packet framing is used with the BPSK modem. The BPSK packet framing can be configured by Set_PacketParams() command and allows the total frame length definition. The full packet (preamble, synch word, device id to CRC) must be provided in the transmit data buffer.
Page 124: Receive Data Buffer Operation
Sub-GHz radio (SUBGHZ) RM0461 from the receive data buffer, the offset must be set to the RxBufferPointer value. To write to the first byte in the transmit data buffer, the offset must be set to the TxBaseAddr value. The RAM data buffer has a circular nature: any address increment exceeding 0xFF wraps around to address 0x00.
Page 125: Figure 11. Sub-Ghz Radio Operating Modes
RM0461 Sub-GHz radio (SUBGHZ) – RC 64 kHz and timers can be kept running (optional) – Optional registers and data memory retained • Calibration mode – intermediate mode between Deep-Sleep or Sleep, and Standby – used to calibrate the sub-GHz radio RC 64 kHz, sub-GHz radio RC 13 MHz, RF- PLL, RF-ADC and image •...
Page 126: Startup Mode
Sub-GHz radio (SUBGHZ) RM0461 4.7.1 Startup mode At POR or after a sub-GHz radio reset, the Startup mode is entered. BUSY is set. When internal supply and clocks become available, the sub-GHz radio enters Sleep mode. 4.7.2 Sleep mode In Sleep mode, only the sub-GHz radio startup and Sleep control is operational and the configuration is lost.
Page 127: Standby Mode
RM0461 Sub-GHz radio (SUBGHZ) When in Standby mode, the calibration of different blocks can be requested by Calibrate() command. Image calibration for specific frequency bands The image calibration is performed as part of the calibration process, by default in the band 902 - 928 MHz.
Page 128: Receive Mode (Rx)
Sub-GHz radio (SUBGHZ) RM0461 When entering TX mode, BUSY is set. In TX mode, BUSY is cleared when the PA ramped up and preamble transmission starts. PA ramping The PA ramping time can be selected while setting the output power, by Set_TxParams(). 4.7.7 Receive mode (RX) The RX mode can be requested to be entered from Standby mode.
Page 129: Sub-Ghz Radio Spi Interface
RM0461 Sub-GHz radio (SUBGHZ) BUSY timing is shown in the figure below. Figure 12. Sub-GHz radio BUSY timing BUSY Opcode Param 1 Param n Write command SWMODE MSv64330V1 For the different mode transitions, typical busy timing values are given in the table below. Table 25.
Page 130: Sub-Ghz Radio Command Structure
Sub-GHz radio (SUBGHZ) RM0461 For each access, the sub-GHz radio SPI NSS goes low at the start of the transfer and is set high at the end, after all bytes have been transfered. The following transaction types are supported: • configuration transaction: provides the CPU with a direct access to control registers.
Page 131 RM0461 Sub-GHz radio (SUBGHZ) byte 0 bits 7:0 Opcode: 0x0D bytes 2:1 bits 15:0 Addr[15:0]: first write address byte 3 bits 7:0 Data0[7:0]: data to write to first address byte n+3 bits 7:0 Datan[7:0]: data to write to address + n (n = number of bytes to write) Read_Register() command Read_Register(Addr, Status, Data0, Data1, to Datan) allows a block of bytes to be read in a contiguous memory area starting from the specified address.
Page 132: Operating Mode Commands
Sub-GHz radio (SUBGHZ) RM0461 offset. The offset is auto incremented after each byte. When the offset exceeds the value 255, it is wrapped around to 0 (providing a 256 byte circular buffer). Opcode Offset[7:0] Status[7:0] Data0[7:0] Datan[7:0] byte 0 bits 7:0 Opcode: 0x1E byte 1 bits 7:0 Offset[7:0]: first read address offset byte 2...
Page 133 RM0461 Sub-GHz radio (SUBGHZ) Set_Standby() command Set_Standby(StandbyCfg) is used to set the sub-GHz radio in Standby mode. The StandbyCfg parameter allows some optional functions to be selected in Standby mode. Opcode StandbyCfg byte 0 bits 7:0 Opcode: 0x80 byte 1 bits 7:1 Reserved, must be kept at reset value.
Page 134 Sub-GHz radio (SUBGHZ) RM0461 Set_Rx() command Set_Rx(Timeout) is used to set the sub-GHz radio in Receive mode. Opcode Timeout[23:0] byte 0 bits 7:0 Opcode: 0x82 bytes 3:1 bits 23:0 Timeout[23:0]: Transmit packet timeout 0x000000: timeout disabled 0x000001 - 0xFFFFFE: timeout enabled, single packet receive mode, resolution 15.625 μs 0xFFFFFF: timeout disabled, continuous receive mode Time-out duration is computed by the following formula:...
Page 135: Figure 13. Receiver Listening Mode Timing
RM0461 Sub-GHz radio (SUBGHZ) The following steps are performed: Save sub-GHz radio configuration. Enter Receive mode and listen for a preamble for the specified RxPeriod period. Upon the detection of a preamble, the RxPeriod timeout is stopped and restarted with the value 2 x RxPeriod +SleepPeriod.
Page 136 Sub-GHz radio (SUBGHZ) RM0461 Set_Cad() command Set_Cad() is used to detect the channel activity and can only be used with LoRa packet types. The channel activity detection (CAD) is a specific LoRa operation mode, where the sub-GHz radio searches for a LoRa radio signal. After the search is completed, the Standby mode is automatically entered, CAD is done and IRQ is generated.
Page 137: Sub-Ghz Radio Configuration Commands
RM0461 Sub-GHz radio (SUBGHZ) 4.8.4 Sub-GHz radio configuration commands Set_PacketType() command Set_PacketType(PktType) allows the selection of packet frame format. This command must be the first command of a sub-GHz radio configuration sequence. Changing from one sub-GHz radio configuration to another is done using Set_PacketType().
Page 138 Sub-GHz radio (SUBGHZ) RM0461 Set_RfFrequency() command Set_RfFrequency(RfFreq) is used to lock the RF-PLL frequency to the transmit and receive frequency. Opcode RfFreq[31:0] byte 0 bits 7:0 Opcode: 0x86 bytes 4:1 bits 31:0 RfFreq[31:0]: RF frequency RF-PLL frequency = 32e x RFfreq / 2 Set_TxParams() command Set_TxParams(Power, RampTime) is used to set the transmit output power and the PA ramp-up time.
Page 139: Table 27. Pa Optimal Setting And Operating Modes
RM0461 Sub-GHz radio (SUBGHZ) Set_PaConfig() command Set_PaConfig(PaDutyCycle, HpMax, PaSel, 0x01) is used to customize the maximum output power and PA efficiency. Opcode PaDutyCycle[2:0] HpMax[2:0] PaSel 0x01 byte 0 bits 7:0 Opcode: 0x95 byte 1 bits 7:3 Reserved, must be kept at reset value. bits 2:0 PaDutyCycle[2:0]: PA duty cycle (conduit angle) control Duty cycle = 0.2 + 0.04 x PaDutyCycle[2:0] (see Table 27...
Page 140 Sub-GHz radio (SUBGHZ) RM0461 Set_TxRxFallbackMode() command Set_TxRxFallbackMode(FallbackMode) defines the operating mode to enter after a successful packet transmission or packet reception. Opcode FallbackMode[7:0] byte 0 bits 7:0 Opcode: 0x93 byte 1 bits 7:0 FallbackMode[7:0]: Fall-back mode after successful packet transmission or packet reception 0x20: Standby mode entry (default) 0x30: Standby with HSE32 enabled mode entry...
Page 141: Table 28. Recommended Cad Configuration Settings
RM0461 Sub-GHz radio (SUBGHZ) byte 4 bits 7:1 Reserved, must be kept at reset value. Bit 0 CadExitMode: defines the sub-GHz radio operating mode to enter after CAD scan is finished 0: Standby with RC 13 MHz mode entry after CAD, whatever is detected during the CAD scan 1: Standby with RC 13 MHz mode after CAD if no LoRa symbol is detected during the CAD scan...
Page 142 Sub-GHz radio (SUBGHZ) RM0461 type in Set_PacketType() sent prior to this function, the parameters for generic packets are interpreted as follows: • Br and Fdev are used for the transmission and reception. • Bw is used only for reception. • PulseShape represents the Gaussian filter that can be used to filter the modulation stream at the transmitter.
Page 143 RM0461 Sub-GHz radio (SUBGHZ) bytes5 bit 7:0 Bw[7:0]: Bandwidth 0x1F: BW4 4.8 kHz DSB 0x17: BW5 5.8 kHz DSB 0x0F: BW7 7.3 kHz DSB 0x1E: BW9 9.7 kHz DSB 0x16: BW11 11.7 kHz DSB 0x0E: BW14 14.6 kHz DSB 0x1D: BW19 19.5 kHz DSB 0x15: BW23 23.4 kHz DSB 0x0D: BW29 29.3 kHz DSB 0x1C: BW39 39.0 kHz DSB...
Page 144 Sub-GHz radio (SUBGHZ) RM0461 byte 2 bits 7:0 Bw[7:0]: Bandwidth 0x00: bandwidth 7 (7.81 kHz) 0x08: bandwidth 10 (10.42 kHz) 0x01: bandwidth 15 (15.63 kHz) 0x09: bandwidth 20 (20.83 kHz) 0x02: bandwidth 31 (31.25 kHz) 0x0A: bandwidth 41 (41.67 kHz) 0x03: bandwidth 62 (62.50 kHz) 0x04: bandwidth 125 (125 kHz) 0x05: bandwidth 250 (250 kHz)
Page 145 RM0461 Sub-GHz radio (SUBGHZ) Generic Set_PacketParams() command Set_PacketParams(PbLength,PbDetLength,SynchWordLength,AddrComp, PktType,PayloadLength,CrcType,Whitening) is used to configure the packet handling for the sub-GHz radio. When the generic packet is selected with packet type in Set_PacketType() sent prior to this function, the parameters are interpreted as below. Opcode PbLength[15:0] PktType...
Page 146 Sub-GHz radio (SUBGHZ) RM0461 byte 8 bits 7:3 Reserved, must be kept at reset value. bits 2:0 CrcType[2:0]: CRC type definition The CRC initialization value is provided in SUBGHZ_GCRCINIRL and SUBGHZ_GCRCINIRH. The polynomial is defined in SUBGHZ_GCRCPOLRL and SUBGHZ_GCRCPOLRH. 0x0: 1-byte CRC 0x1: no CRC 0x2: 2-byte CRC 0x4: 1-byte inverted CRC...
Page 147 RM0461 Sub-GHz radio (SUBGHZ) byte 5 bits 7:1 Reserved, must be kept at reset value. bit 0 CrcType CRC enable 0: CRC disabled 1: CRC enabled byte 6 bits 7:1 Reserved, must be kept at reset value. bit 0 InvertIQ: IQ setup 0: standard IQ setup 1: inverted IQ setup BPSK Set_PacketParams() command...
Page 148: Communication Status Information Commands
Sub-GHz radio (SUBGHZ) RM0461 4.8.5 Communication status information commands Get_Status() command Get_Status(Status) can be issued at any time. Opcode Status[7:0] byte 0 bits 7:0 Opcode: 0xC0 byte 1 bit 7 Reserved, must be kept at reset value. bits 6:4 Status_Mode[2:0] sub-GHz radio operating mode 0x2: Standby mode with RC 13 MHz 0x3: Standby mode with HSE32 0x4: FS mode...
Page 149 RM0461 Sub-GHz radio (SUBGHZ) (G)FSK Get_PacketStatus() command Get_PacketStatus(Status, RxStatus, RssiSync, RssiAvg) returns information on the last received packet. Depending on the selected packet type in Set_PacketType() sent prior to this function, the parameters for generic packets are interpreted as below. Opcode Status[7:0] RxStatus[7:0]...
Page 150 Sub-GHz radio (SUBGHZ) RM0461 Get_RssiInst() command Get_RssiInst(Status, RssiInst) returns the instantaneous signal strength during packet reception. Opcode Status[7:0] RssiInst[7:0] byte 0 bits 7:0 Opcode: 0x15 byte 1 bits 7:0 Status[7:0]: see Get_Status() command byte 2 bits 7:0 RssiInst[7:0]: instantaneous RSSI level at the reception time Signal power = - RssiInst / 2 (in dBm) (G)FSK Get_Stats() command Get_Stats(Status, NbPktReceived, NbPktCrcError, NpPktLengthError)
Page 151: Irq Interrupt Commands
RM0461 Sub-GHz radio (SUBGHZ) bytes 3:2 bits 15:0 NbPktReceived[15:0]: Number of packets received bytes 5:4 bits 15:0 NbPktCrcError[15:0]: Number of packets received with a payload CRC error. bytes 7:6 bits 15:0 NbPktHeaderError[15:0]: Number of packets received with a header CRC error Reset_Stats() command Reset_Stats(0x00,0x00,0x00,0x00,0x00,0x00) resets the received packet...
Page 152 Sub-GHz radio (SUBGHZ) RM0461 Table 29. IRQ bit mapping and definition (continued) Source Description Packet type Operation preamble, syncword, address, GFSK CRC or length error CrcErr CRC error LoRa CadDone Channel activity detection finished LoRa CadDetected Channel activity detected LoRa Timeout RX or TX timeout LoRa and GFSK...
Page 153: Miscellaneous Commands
RM0461 Sub-GHz radio (SUBGHZ) byte 0 bits 7:0 Opcode: 0x12 byte 1 bits 7:0 Status[7:0]: see Get_Status() command bytes 3:2 bits 15:0 IrqStatus[15:0]: interrupt pending status information Table 29 for interrupt bit map definition. For each bit: 0: IRQ not pending 1: IRQ pending Clr_IrqStatus() command Clr_IrqStatus(ClrIrq) clears the IRQ status flags (IrqStatus[15:0]).
Page 154: Table 30. Image Calibration For Ism Bands
Sub-GHz radio (SUBGHZ) RM0461 byte 1 bit 7 Reserved, must be kept at reset value. bit 6 CalibCfg_Image: Image calibration 0: Image calibration disabled 1: Image calibration enabled bit 5 CalibCfg_AdcBulkP: RF-ADC bulk P calibration 0: RF-ADC bulk P calibration disabled 1: RF-ADC bulk P calibration enabled bit 4 CalibCfg_AdcBulkN: RF-ADC bulk N calibration 0: RF-ADC bulk N calibration disabled...
Page 155 RM0461 Sub-GHz radio (SUBGHZ) Opcode CalFreq1[7:0] CalFreq2[7:0] byte 0 bits 7:0 Opcode: 0x98 byte 1 bits 7:0 CalFreq1[7:0]: Lower frequency of the band to calibrate (see Table byte 2 bits 7:0 CalFreq2[7:0]: Higher frequency of the band to calibrate (see Table The calibration frequencies are computed as follows: Calibration...
Page 156: Set_Tcxomode Command
Sub-GHz radio (SUBGHZ) RM0461 byte 0 bits 7:0 Opcode: 0x17 byte 1 bits 7:0 Status[7:0]: see Get_Status() command bytes 3:2 bits 15:9 Reserved, must be kept at reset value. bit 8 OpError_PaRampError: PA ramping failed bit 7 Reserved, must be kept at reset value. bit 6 OpError_PllLockError: RF-PLL locking failed bit 5 OpError_XoscStartError: HSE32 clock startup failed bit 4 OpError_ImageCalibrationError: Image calibration failed...
Page 157: Sub-Ghz Radio Commands Overview
RM0461 Sub-GHz radio (SUBGHZ) The definition of RegTcxoTrim and Timeout bytes is given in the table below. Table 32. RegTcxoTrim and Timeout bytes definition Byte 1 [7:3] Byte 1 RegTcxoTrim[2:0 ] (V) Byte 2-4 [23:0] timeout 0x0 = 1.6 0x000000 = timeout disabled 0x1 = 1.7 Other = timeout enabled 0x2 = 1.8...
Page 158 Sub-GHz radio (SUBGHZ) RM0461 Table 33. Sub-GHz radio SPI commands overview (continued) Command Opcode Parameters 0xC0 Status Get_Status() 0x1E Offset, Status, Data0, Data1, ..., Datan Read_Buffer() 0x1D Addr, Status, Data0, Data1, ..., Datan Read_Register() 0x00 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 Reset_Stats() 0x8F TxBaseAddr, RxBaseAddr...
Page 159: Sub-Ghz Radio Application Configuration
RM0461 Sub-GHz radio (SUBGHZ) Sub-GHz radio application configuration The sub-GHz radio is controlled via the SPI command interface. The following sections describe the basic sequence for some sub-GHz radio operations. After releasing the sub-GHz radio reset and waking it up with sub-GHz radio SPI NSS, the sub-GHz radio automatically performs a calibration and enters Standby mode.
Page 160: Basic Sequence For Lora And (G)Fsk Receive Operation
Sub-GHz radio (SUBGHZ) RM0461 4.9.2 Basic sequence for LoRa and (G)FSK receive operation The sub-GHz radio can be set in LoRa or (G)FSK receive operation mode with the following steps: Define the location where the received payload data must be stored in the data buffer, with Set_BufferBaseAddress().
Page 161: Basic Sequence For Bpsk Transmit Operation
RM0461 Sub-GHz radio (SUBGHZ) 4.9.3 Basic sequence for BPSK transmit operation The sub-GHz radio can be set in BPSK transmit operation mode by the following steps: Define the location of the transmit payload data in the data buffer, with Set_BufferBaseAddress() Write the packet data (synchronization word, payload data) to the transmit data buffer with Write_Buffer().
Page 162: Sub-Ghz Radio Ramp-Up Lsb Register (Subghz_Ram_Rampupl)
Sub-GHz radio (SUBGHZ) RM0461 4.10.2 Sub-GHz radio ramp-up LSB register (SUBGHZ_RAM_RAMPUPL) Address offset: 0x0F1 Reset value: 0x00 RAMPUP[7:0] Bits 7:0 RAMPUP[7:0]: Ramp-up LSB bits 4.10.3 Sub-GHz radio ramp-down MSB register (SUBGHZ_RAM_RAMPDNH) Address offset: 0x0F2 Reset value: 0x00 RAMPDN[15:8] Bits 7:0 RAMPDN[15:8]: Ramp-down MSB bits 4.10.4 Sub-GHz radio ramp-down LSB register (SUBGHZ_RAM_RAMPDNL)
Page 163: Sub-Ghz Radio Frame Limit Lsb Register (Subghz_Ram_Frameliml)
RM0461 Sub-GHz radio (SUBGHZ) 4.10.6 Sub-GHz radio frame limit LSB register (SUBGHZ_RAM_FRAMELIML) Address offset: 0x0F5 Reset value: 0x00 FRAMELIML[7:0] Bits 7:0 FRAMELIML[7:0]: frame limit LSB bits 4.10.7 Sub-GHz radio generic bit synchronization register (SUBGHZ_GBSYNCR) Address offset: 0x6AC Reset value: 0x00 This register must be cleared to 0x00 when using packet types other than LoRa.
Page 164: Sub-Ghz Radio Generic Cfo Lsb Register (Subghz_Gcforl)
Sub-GHz radio (SUBGHZ) RM0461 Bits 7:4 Reserved, must be kept at reset value. Bits 3:0 DEMOD_CFO[3:0]: actual frequency error from normalized value (MSB bits) 4.10.9 Sub-GHz radio generic CFO LSB register (SUBGHZ_GCFORL) Address offset: 0x6B1 Reset value: 0x00 DEMOD_CFO[7:0] Bits 7:0 DEMOD_CFO[7:0]: actual frequency error from normalized value (LSB bits) 4.10.10 Sub-GHz radio generic packet control 1 register (SUBGHZ_GPKTCTL1R)
Page 165: Sub-Ghz Radio Generic Whitening Lsb Register
RM0461 Sub-GHz radio (SUBGHZ) Bit 4 CONTTX: Generic packet continuous transmit enable Bits 3:2 INFSEQSEL[1:0]: Generic packet infinite sequence selection 00: preamble 0x5555 01: all zero 0x0000 10: all one 0xFFFF 11: PRBS9 Bit 1 INFSQEQEN: Generic packet infinite sequence enable Bit 0 WHITEINI[8]: Generic packet whitening initial value MSB bit [8] 4.10.12 Sub-GHz radio generic whitening LSB register...
Page 166: Sub-Ghz Radio Generic Crc Initial Lsb Register
Sub-GHz radio (SUBGHZ) RM0461 4.10.15 Sub-GHz radio generic CRC initial LSB register (SUBGHZ_GCRCINIRL) Address offset: 0x6BD Reset value: 0x0F CRCINI[7:0] Bits 7:0 CRCINI[7:0]: Generic packet CRC initial polynomial LSB bits [7:0] These bits are used for CRC initialization. 4.10.16 Sub-GHz radio generic CRC polynomial MSB register (SUBGHZ_GCRCPOLRH) Address offset: 0x6BE Reset value: 0x10...
Page 167: Sub-Ghz Radio Generic Synchronization Word Control Register 7
RM0461 Sub-GHz radio (SUBGHZ) 4.10.18 Sub-GHz radio generic synchronization word control register 7 (SUBGHZ_GSYNCR7) Address offset: 0x6C0 Reset value: 0x97 SYNCWORD[63:56] Bits 7:0 SYNCWORD[63:56]: Eight byte of generic packet synchronization word 4.10.19 Sub-GHz radio generic synchronization word control register 6 (SUBGHZ_GSYNCR6) Address offset: 0x6C1 Reset value: 0x23...
Page 168 Sub-GHz radio (SUBGHZ) RM0461 4.10.22 Sub-GHz radio generic synchronization word control register 3 (SUBGHZ_GSYNCR3) Address offset: 0x6C4 Reset value: 0x56 SYNCWORD[31:24] Bits 7:0 SYNCWORD[31:24] Fourth byte of generic packet synchronization word 4.10.23 Sub-GHz radio generic synchronization word control register 2 (SUBGHZ_GSYNCR2) Address offset: 0x6C5 Reset value: 0x53...
Page 169 RM0461 Sub-GHz radio (SUBGHZ) 4.10.26 Sub-GHz radio generic node address register (SUBGHZ_GNODEADR) Address offset: 0x6CD Reset value: 0x00 NODEADD[7:0] Bits 7:0 NODEADD[7:0]: Node address used in FSK mode register 4.10.27 Sub-GHz radio generic broadcast address register (SUBGHZ_GBCASTADDR) Address offset: 0x6CE Reset value: 0x00 BCASTADD[7:0] Bits 7:0 BCASTADD[7:0]: Broadcast address used in FSK mode register...
Page 170 Sub-GHz radio (SUBGHZ) RM0461 4.10.30 Sub-GHz radio synchro timeout register (SUBGHZ_LSYNCTIMEOUTR) Address offset: 0x706 Reset value: 0x00 SYNCTIMEOUT[7:0] Bits 7:0 SYNCTIMEOUT[7:0]: TimeoutValue = synchtimeout[7:3]*2^(2*synchtimeout[2:0]+1) If a detection has not occurred by TimeoutValue, it goes back to Standby mode, or restart synch in continuous receive mode Bits 7:3 synchtimeout(7:3) mantissa part Bits 2:0 synchtimeout(2:0) exponent part...
Page 171 RM0461 Sub-GHz radio (SUBGHZ) Bits 7:0 SYNCWORD[15:8]: LoRa synchronization word MSB bits [15:8] 0x14: LoRa private network 0x34: LoRa public network Others: reserved 4.10.34 Sub-GHz radio LoRa synchronization word LSB register (SUBGHZ_LSYNCRL) Address offset: 0x741 Reset value: 0x24 SYNCWORD[7:0] Bits 7:0 SYNCWORD[7:0]: LoRa synchronization word LSB bits [7:0] 0x24: LoRa private network 0x44: LoRa public network Others: reserved...
Page 172 Sub-GHz radio (SUBGHZ) RM0461 4.10.37 Sub-GHz radio bandwidth select register (SUBGHZ_BWSELR) Address offset: 0x807 Reset value: 0x00 CHBWMANT[1:0] CHBWEXPO[2:0] Bits 7:5 Reserved, must be kept at reset value. Bits 4:3 CHBWMANT[1:0]: Channel bandwidth mantissa Bits 2:0 CHBWEXP[2:0]: Channel bandwidth exponent 4.10.38 Sub-GHz radio random number register 3 (SUBGHZ_RNGR3) Address offset: 0x819...
Page 173 RM0461 Sub-GHz radio (SUBGHZ) 4.10.41 Sub-GHz radio random number register 0 (SUBGHZ_RNGR0) Address offset: 0x81C Reset value: 0x00 RNDATA[7:0] Bits 7:0 RNDATA[7:0]: Random number data bits [7:0] 4.10.42 Sub-GHz radio SD resolution register (SUBGHZ_SDCFG0R) Address offset: 0x889 Reset value: 0x00 SD[7:0] Bits 7:0 SD[7:0]: Radio SD resolution 4.10.43...
Page 174 Sub-GHz radio (SUBGHZ) RM0461 Bits 7:2 SENSI_ADJUST[5:0]: Sensitivity Floor of AGC This bitfield must be kept at 0x25. Bits 1:0 PMODE[1:0]: Receiver power mode selection between normal mode and power saving mode 00: power saving mode (reduced sensitivity) 01: boost mode level1 active (improves sensitivity at detriment of power consumption) 10: boost mode level2 active (improves a set further sensitivity at detriment of power consumption) Others: boost mode (best receiver sensitivity)
Page 175: Sub-Ghz Radio Disable Mixer Register (Reg_Ana_Mixer)
RM0461 Sub-GHz radio (SUBGHZ) 4.10.48 Sub-GHz radio disable LNA register (REG_ANA_LNA) Address offset: 0x8E2 Reset value: 0x00 Bits 7:0 Reserved, must be kept at reset value. 4.10.49 Sub-GHz radio disable mixer register (REG_ANA_MIXER) Address offset: 0x8E5 Reset value: 0x00 Bits 7:0 Reserved, must be kept at reset value. 4.10.50 Sub-GHz radio PA over current protection register (SUBGHZ_PAOCPR)
Page 176: Sub-Ghz Radio Rtc Period Msb Register (Subghz_Rtcprdr2)
Sub-GHz radio (SUBGHZ) RM0461 Bits 7:1 Reserved, must be kept at reset value. Bit 0 RTCEN: Writing 1 restarts the radio RTC. 4.10.52 Sub-GHz radio RTC period MSB register (SUBGHZ_RTCPRDR2) Address offset: 0x906 Reset value: 0x00 RTCPRD[31:16] Bits 7:0 RTCPRD[31:16]: Updates radio RTC period (MSB) 4.10.53 Sub-GHz radio RTC period mid-byte register (SUBGHZ_RTCPRDR1)
Page 177: Sub-Ghz Radio Hse32 Osc_In Capacitor Trim Register
RM0461 Sub-GHz radio (SUBGHZ) 4.10.55 Sub-GHz radio HSE32 OSC_IN capacitor trim register (SUBGHZ_HSEINTRIMR) Address offset: 0x911 Reset value: 0x12 This register is retained in Sleep mode, but lost in Deep-Sleep mode. Res. Res. TRIM[5:0] Bits 7:6 Reserved, must be kept at reset value. Bits 5:0 TRIM[5:0]: HSE32 XTAL mode OSC_IN load capacitor trimming Load capacitor trimming step size ~0.47 pf.
Page 178: Sub-Ghz Radio Smps Control 0 Register (Subghz_Smpsc0R)
Sub-GHz radio (SUBGHZ) RM0461 4.10.57 Sub-GHz radio SMPS control 0 register (SUBGHZ_SMPSC0R) Address offset: 0x916 Reset value: 0x00 Res. CLKDE Res. Res. Res. Res. Res. Res. Bit 7 Reserved, must be kept at reset value. Bit 6 CLKDE: SMPS clock detection enable SMPS clock detection must be enabled before enabling the SMPS, if the application uses an external HSE clock source (not coming from XO or TCXO but from another device).
Page 179: Sub-Ghz Radio Rtc Control Register (Subghz_Eventmaskr)
RM0461 Sub-GHz radio (SUBGHZ) DRV[1:0] Bits 7:3 Reserved, must be kept at reset value. Bits 2:1 DRV[1:0]: SMPS maximum drive capability. 0x0: 20 mA 0x1: 40 mA 0x2: 60 mA 0x3: 100 mA (default) Bit 0 Reserved, must be kept at reset value. 4.10.60 Sub-GHz radio RTC control register (SUBGHZ_EVENTMASKR) Address offset: 0x944...
Page 180 Sub-GHz radio (SUBGHZ) RM0461 Table 34. SUBGHZ register map and reset values (continued) Offset Register name SUBGHZ_GCRCPOLRL CRCPOL[7:0] 0x6BF Reset value SUBGHZ_GSYNCR7 SYNCWORD[63:56] 0x6C0 Reset value SUBGHZ_GSYNCR6 SYNCWORD[55:48] 0x6C1 Reset value SUBGHZ_GSYNCR5 SYNCWORD[47:40] 0x6C2 Reset value SUBGHZ_GSYNCR4 SYNCWORD[39:32] 0x6C3 Reset value SUBGHZ_GSYNCR3 SYNCWORD[31:24] 0x6C4...
Page 181 RM0461 Sub-GHz radio (SUBGHZ) Table 34. SUBGHZ register map and reset values (continued) Offset Register name 0x913- Reserved Reserved 0x915 SUBGHZ_SMPSC0R Res. CLKDE Res. Res. Res. Res. Res. Res. 0x916 Reset value 0x917- Reserved Reserved 0x919 SUBGHZ_PCR Res. CLV[1:0] Res. Res.
Page 182: Power Control (Pwr)
Power control (PWR) RM0461 Power control (PWR) Power supplies The STM32WLEx devices require a V operating voltage supply between 1.71 V and 3.6 V. Several independent supplies (V ) can be provided for DDSMPS FBSMPS DDRF specific peripherals: • = 1.71 V to 3.6 V is the external power supply for the I/Os, the system analog blocks such as reset, power management, internal clocks and low-power regulator.
Page 183: Figure 14. Power Supply Overview
RM0461 Power control (PWR) VREF+ pin is not available on all packages. When not available, this pin is internally bonded to VDDA. When VREF+ is double-bonded with VDDA in a package, the internal voltage reference buffer is not available and must be kept disabled (refer to the datasheet for pinout descriptions).
Page 184: Figure 15. Supply Configurations
Power control (PWR) RM0461 The different supply configurations are shown in the figure below. Figure 15. Supply configurations DDSMPS DDSMPS LDO/SMPS LDO/SMPS LXSMPS LXSMPS FBSMPS FBSMPS DDRF1V5 DDRF1V5 LDO/SMPS supply LDO supply MSv50974V1 The LDO or SMPS step-down converter operating mode can be configured by one of the following: •...
Page 185: Independent Analog Peripherals Supply
RM0461 Power control (PWR) The inrush current of the LDO and SMPS step-down converter can be controlled via the sub- GHz radio SUBGHZ_PCR register. This information is retained in all but the sub-GHz radio Deep-Sleep mode. For more details see Section 4: Sub-GHz radio (SUBGHZ).
Page 186 Power control (PWR) RM0461 The VBAT pin powers RTC, TAMP, the LSE oscillator and the PC13 to PC15 I/Os, allowing RTC and TAMP to operate even when the main power supply is turned off. The switch to the supply is controlled by the power-down reset embedded in the reset block. Warning: During (temporization at V...
Page 187: Voltage Regulator
RM0461 Power control (PWR) VBAT battery charging When V is present, It is possible to charge the external battery on VBAT through an internal resistance. The VBAT charging is done either through a 5 kΩ resistor or through a 1.5 kΩ resistor, depending on the VBRS bit value in the PWR control register 4 (PWR_CR4).
Page 188: Power Supply Supervisor
Power control (PWR) RM0461 Dynamic voltage scaling to decrease V is known as “undervolting”. It is used to save CORE power, particularly in laptop and other mobile devices where the energy comes from a battery and is thus limited. • range 1: high-performance range The main regulator provides a typical output voltage at 1.2 V.
Page 189: Programmable Voltage Detector (Pvd)
RM0461 Power control (PWR) Figure 16. Brownout reset waveform BORH rise hysteresis BORH fall nPwr MS44480V1 1. The reset temporization t is present only for the BOR lowest threshold (V RSTTEMPO BOR0 5.2.2 Programmable voltage detector (PVD) The PVD can be used to monitor V by comparing it to a threshold selected by the PLS[2:0] bits in the PWR control register 2...
Page 190: Peripheral Voltage Monitoring (Pvm)
Power control (PWR) RM0461 Figure 17. PVD thresholds , or PVD_IN rise hysteresis fall PVDO PVDE SW enable PDR reset MS44481V1 5.2.3 Peripheral voltage monitoring (PVM) Only V is monitored by default as it is the only supply required for all system-related functions.
Page 191: Radio End Of Life (Eol)
RM0461 Power control (PWR) The independent supply V is not considered as present by default and a logical and electrical isolation is applied to ignore any information coming from the peripherals supplied by these dedicated supplies: • If V is shorted externally to V , the application must assume that V is available without enabling any peripheral voltage monitoring.
Page 192: Figure 19. Radio Busy Management
Power control (PWR) RM0461 the SUBGHZSPI_NSS activity, and masks the RFBUSYS status low time (not busy) after an SPI command transfer (see the figure below). Figure 19. Radio busy management SUBGHZSPI_DATA SUBGHZSPI_NSS RFBUSY/RFBUSYS RFBUSYMS minimum RFBUSYSM delay EXTI RFBUSY interrupt (Stop, Run) WRFBUSYF wakeup (from Standby) MSv50975V1 At reset, the radio is busy (as signaled by the RFBUSY signal).
Page 193: Low-Power Modes
RM0461 Power control (PWR) Low-power modes By default, the microcontroller is in Run mode after a system or a power reset. Low-power modes are available to save power when the CPU does not need to be kept running, for example when it is waiting for an external event. The user must select the mode giving the best compromise between consumption, startup time and available wakeup sources.
Page 194: Table 36. Low-Power Mode Summary
Power control (PWR) RM0461 powered off. All clocks in the V domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled. CORE LSI and LSE can be kept running. Th RTC can remain active (Standby mode with RTC, Standby mode without RTC). The sub-GHz radio and the PVD may also remain active when enabled independent from the CPU.
Page 195: Table 37. Functionalities Depending On System Operating Mode
RM0461 Power control (PWR) Table 36. Low-power mode summary (continued) Voltage Wakeup Wakeup regulators Mode name Entry Effect on clocks source system clock LPMS = 0b000 + SLEEPDEEP bit Stop 0 + WFI or return from ISR or WFE HSI16 when LPMS = 0b001 + Any EXTI line STOPWUCK = 1 in...
Page 196 Power control (PWR) RM0461 Table 37. Functionalities depending on system operating mode (continued) Stop 0 Stop 1 Stop 2 Standby Shutdo Peripheral Flash memory (up to 256 Kbytes) Flash memory interface SRAM1 SRAM2 Backup registers Brownout reset (BOR) Programmable voltage detector (PVD) Peripheral voltage monitor (PVM3)
Page 197 RM0461 Power control (PWR) Table 37. Functionalities depending on system operating mode (continued) Stop 0 Stop 1 Stop 2 Standby Shutdo Peripheral VREFBUF COMPx (x = 1, 2) Temperature sensor Timers (TIMx) x = 1, 2, 16, 17) LPTIM1 LPTIMx (x = 2, 3) Independent watchdog (IWDG) Window watchdog (WWDG)
Page 198: Table 38. Mcu And Sub-Ghz Radio Operating Modes
Power control (PWR) RM0461 11. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode. 12. The I/Os with wakeup from Standby/Shutdown capability are PA0, PC13 and PB3. 13. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode, but the configuration is lost when exiting the Shutdown mode.
Page 199: Run Mode
RM0461 Power control (PWR) 5.4.1 Run mode Slowing down system clocks In Run mode, the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down the peripherals before entering the Sleep mode.
Page 200: Enter Low-Power Mode
Power control (PWR) RM0461 Enter LPRun mode To enter the LPRun mode, proceed as follows (refer to Table 39): Jump into the SRAM and power down the flash memory by setting the FPDR bit in the Section 5.5.1: PWR control register 1 (PWR_CR1) (optional).
Page 201: Sleep Mode
RM0461 Power control (PWR) register) must be cleared. Only NVIC interrupts with sufficient priority wake up and interrupt the CPU. – Wakeup generated by an NVIC IRQ with SEVONPEND = 1 in the CPU system control register, enabling an interrupt in the peripheral control register and optionally in the NVIC When the CPU resumes from WFE, the peripheral interrupt pending bit and when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear...
Page 202: Low-Power Sleep Mode (Lpsleep)
Power control (PWR) RM0461 Exit Sleep mode The MCU exits the Sleep mode (see Table 41) as indicated in Exit low-power mode. Table 41. Sleep mode Sleep mode Description WFI (wait for interrupt) or WFE (wait for event) while: – SLEEPDEEP = 0 –...
Page 203: Stop 0 Mode
RM0461 Power control (PWR) The table below details how to exit the LPSleep mode. Table 42. LPSleep LPSleep mode Description LPSleep mode is entered from the LPRun mode. WFI (wait for interrupt) or WFE (wait for event) while: – SLEEPDEEP = 0 –...
Page 204 Power control (PWR) RM0461 Enter Stop 0 mode The Stop 0 mode is entered according Section 5.4.3, when the SLEEPDEEP bit in the Cortex system control register is set (see Table 43). If flash memory programming is ongoing, the Stop 0 mode entry is delayed until the operation is completed.
Page 205: Stop 1 Mode
RM0461 Power control (PWR) When exiting the Stop 0 mode, the MCU is either in Run mode (range 1 or range 2 depending on VOS bit in PWR control register 1 (PWR_CR1)) or in LPRun mode if the bit LPR is set in the same register. Table 43.
Page 206: Stop 2 Mode
Power control (PWR) RM0461 REGLPS bit can be used to check that the low-power regulator is ready (see the table below). Table 44. Stop 1 mode Stop 1 Description WFI (wait for interrupt) or WFE (wait for event) while: – SLEEPDEEP bit is set in Cortex system control register –...
Page 207 RM0461 Power control (PWR) The BOR is always available in Stop 2 mode. The consumption is increased when thresholds higher than V are used. BOR0 The BOR and PDR can be activated to sample periodically the supply voltage. This option enabled by setting the ULPEN bit of the PWR_CR3 register allows the current consumption to be decreased in this mode, but any drop of the voltage below the operating conditions between two active periods of the supply detector, results in a non-generation of PDR reset.
Page 208: Standby Mode
Power control (PWR) RM0461 Table 45. Stop 2 mode Stop 2 Description WFI (wait for interrupt) or WFE (wait for event) while: – SLEEPDEEP bit is set in Cortex system control register – No interrupt (for WFI) or event (for WFE) is pending –...
Page 209 RM0461 Power control (PWR) The RTC output on PC13 only is functional in Standby mode. PC14 and PC15 used for LSE are also functional. Three wakeup pins (WKUPx, x = 1, 2, 3) and the three TAMP tampers are available. The sub-GHz radio is functional and PVD can be enabled.
Page 210: Shutdown Mode
Power control (PWR) RM0461 Refer to the table below for more details on how to exit Standby mode. Table 46. Standby mode Standby Description WFI (wait for interrupt) or WFE (wait for event) while: – SLEEPDEEP bit is set in Cortex system control register –...
Page 211: Auto-Wakeup From Low-Power Mode
RM0461 Power control (PWR) In Shutdown mode, the following features can be selected by programming individual control bits: • Real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR). Caution: In case of V power-down, the RTC content is lost.
Page 212: Pwr Registers
Power control (PWR) RM0461 following alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the RCC Backup domain control register (RCC_BDCR): • Low-power 32.768 kHz external crystal oscillator (LSE OSC) This clock source provides a precise time base with very low-power consumption. •...
Page 213 RM0461 Power control (PWR) Bits 31:15 Reserved, must be kept at reset value. Bit 14 LPR: LPRun When this bit is set, the supply mode is switched from main regulator mode (MR) to low- power regulator mode (LPR). Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead. Bits 13:11 Reserved, must be kept at reset value.
Page 214: Pwr Control Register 2 (Pwr_Cr2)
Power control (PWR) RM0461 Bit 4 FPDR: Flash memory power-down mode during LPRun This bit can only be written to 1 after unlocking this register bit, by first writing (code 0xC1B0) into this register (when writing the code, the register bits are not updated). Selects whether the flash memory is in power-down mode or Idle mode when in LPRun mode.
Page 215: Pwr Control Register 3 (Pwr_Cr3)
RM0461 Power control (PWR) Bits 3:1 PLS[2:0]: Programmable voltage detector level selection. These bits select the voltage threshold detected by the programmable voltage detector: 000: V around 2.0 V PVD0 001: V around 2.2 V PVD1 010: V around 2.4 V PVD2 011: V around 2.5 V...
Page 216 Power control (PWR) RM0461 Bit 11 EWRFBUSY: radio busy wakeup from Standby for CPU enable When this bit is set, the radio busy is enabled and triggers a wakeup from Standby event to CPUwhen a rising or a falling edge occurs. The active edge is configured via the WRFBUSYP bit in the PWR control register 4 (PWR_CR4).
Page 217: Pwr Control Register 4 (Pwr_Cr4)
RM0461 Power control (PWR) 5.5.4 PWR control register 4 (PWR_CR4) This register is not reset when exiting Standby modes. Access: additional APB cycles are needed to access this register versus those needed for a standard APB access (three for a write and two for a read). Address offset: 0x00C Reset value: 0x0000 0000 Res.
Page 218: Pwr Status Register 1 (Pwr_Sr1)
Power control (PWR) RM0461 5.5.5 PWR status register 1 ( PWR_SR1 ) This register is not reset when exiting Standby modes. Access: two additional APB cycles are needed to read this register versus a standard APB read. Address offset: 0x010 Reset value: 0x0000 0000 Res.
Page 219: Power Status Register 2 (Pwr_Sr2)
RM0461 Power control (PWR) 5.5.6 Power status register 2 (PWR_SR2) This register is partially reset when exiting Standby/Shutdown modes. Address offset: 0x014 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 220 Power control (PWR) RM0461 Bit 7 FLASHRDY: Flash memory ready This bit is set by hardware when the flash memory can be accessed by software after a software controlled flash power down (in LPRun mode). This bit is cleared by hardware when the flash memory is powered down.
Page 221: Pwr Status Clear Register (Pwr_Scr)
RM0461 Power control (PWR) 5.5.7 PWR status clear register (PWR_SCR) Access: three additional APB cycles are needed to write this register versus a standard APB write. Address offset: 0x018 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res.
Page 222: Pwr Control Register 5 (Pwr_Cr5)
Power control (PWR) RM0461 5.5.8 PWR control register 5 (PWR_CR5) This register is not reset when exiting Standby modes. Access: three additional APB cycles are needed to write this register versus a standard APB write. Address offset: 0x01C Reset value: 0x0000 0000 Res.
Page 223: Pwr Port A Pull-Down Control Register (Pwr_Pdcra)
RM0461 Power control (PWR) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PU[15:0]: Port PA[y] pull-up bit y (y = 0 to 15) When set, each bit activates the pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3).
Page 224: Pwr Port B Pull-Down Control Register (Pwr_Pdcrb)
Power control (PWR) RM0461 5.5.12 PWR port B pull-down control register (PWR_PDCRB) This register is not reset when exiting Standby modes. Access: additional APB cycles are needed to access this register versus those needed for a standard APB access (three for a write and two for a read). Address offset: 0x02C Reset value: 0x0000 0000 Res.
Page 225: Pwr Port C Pull-Down Control Register (Pwr_Pdcrc)
RM0461 Power control (PWR) 5.5.14 PWR port C pull-down control register (PWR_PDCRC) This register is not reset when exiting Standby modes. Access: additional APB cycles are needed to access this register versus those needed for a standard APB access (three for a write and two for a read). Address offset: 0x034 Reset value: 0x0000 0000 Res.
Page 226: Pwr Port H Pull-Down Control Register (Pwr_Pdcrh)
Power control (PWR) RM0461 5.5.16 PWR port H pull-down control register (PWR_PDCRH) This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: additional APB cycles are needed to access this register versus those needed for a standard APB access (three for a write and two for a read).
Page 227: Pwr Sub-Ghz Spi Control Register (Pwr_Subghzspicr)
RM0461 Power control (PWR) Bit 10 C1STOPF: System Stop 0, 1 flag for CPU (all core states retained) This bit is set by hardware and cleared only by any reset or by setting C1CSSF bit. 0: System has not been in Stop 0 or 1 mode 1: System has been in Stop 0 or 1 mode.
Page 228: Pwr Register Map
Power control (PWR) RM0461 5.5.19 PWR register map Table 48. PWR register map and reset values Offset Register name LPMS PWR_CR1 [2:0] 0x000 Reset value PWR_CR2 PLS [2:0] 0x004 Reset value PWR_CR3 0x008 Reset value PWR_CR4 0x00C Reset value PWR_SR1 0x010 Reset value PWR_SR2...
Page 229 RM0461 Power control (PWR) Table 48. PWR register map and reset values (continued) Offset Register name PWR_PDCRB 0x02C Reset value PWR_PUCRC 0x030 Reset value PWR_PDCRC 0x034 Reset value PWR_PUCRH 0x058 Reset value PWR_PDCRH 0x05C Reset value PWR_EXTSCR 0x088 Reset value PWR_ SUBGHZSPICR 0x090...
Page 230: Reset And Clock Control (Rcc)
Reset and clock control (RCC) RM0461 Reset and clock control (RCC) Reset There are three types of reset, defined as system reset, power reset and Backup domain reset. 6.1.1 Power reset A power reset is generated when one of the following events occurs: •...
Page 231: Backup Domain Reset
RM0461 Reset and clock control (RCC) In case on an internal reset, the internal pull-up R is deactivated in order to save the power consumption through the pull-up resistor. Figure 20. Simplified diagram of the reset circuit System reset External Filter reset NRST...
Page 232: Sub-Ghz Radio Reset
Reset and clock control (RCC) RM0461 A Backup domain reset is generated when one of the following events occurs: • a software reset, triggered by setting the BDRST bit in the RCC Backup domain control register (RCC_BDCR) • or V power on, if both supplies have previously been powered off A Backup domain reset only affects the LSE oscillator, the RTC, the Backup registers and the RCC Backup domain control register.
Page 233 RM0461 Reset and clock control (RCC) Most peripheral clocks are derived from their bus clock (HCLK, PCLK) except the following: • The clock used for true RNG, is derived (selected by software) from one of the following sources: – PLL VCO (PLLQCLK) (only available in Run mode) –...
Page 234: Hse32 Clock With Trimming
Reset and clock control (RCC) RM0461 – LSI clock – HSE32 clock divided by 32 The functionality in Stop mode (including wakeup) is supported only when the clock is LSI or LSE. • The IWDG clock is always the LSI clock. The RCC feeds the CPU system timer (SysTick) external clock with the AHB clock (HCLK1) divided by eight.
Page 235 RM0461 Reset and clock control (RCC) The high-speed external clock signal (HSE32) can be generated from the following clock sources: • HSE32 external crystal • HSE32 external clock – external clock source – external TCXO The clock source must be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time.
Page 236: Figure 22. Hse32 Clock Sources
Reset and clock control (RCC) RM0461 Figure 22. HSE32 clock sources Clock source Hardware configuration tunable load capacitors LOUT Crystal OSC_IN OSC_OUT OSC_OUT OSC_IN External connected External clock source VDDTCXO OSC_IN OSC_OUT TCXO Not connected Note: Force SUBGHZ_HSEINTRIMR = 0x00 TCXO to get C = 11.3 pF.
Page 237: Hsi16 Clock
RM0461 Reset and clock control (RCC) Figure 23. HSE32 TCXO control VDDRF TCXO PB0-VDDTCXO PB0 GPIO HSEBYPPWR VDD TCXO tcxoon HSEON TCXO HSE32 oscon OSC_IN Radio control Control OSC_OUT NC HSERDY HSEclk Note: Force SUBGHZ_HSEINTRIMR = 0x00 Control to get C = 11.3 pF.
Page 238 Reset and clock control (RCC) RM0461 If the application is subject to voltage or temperature variations, this may affect the RC oscillator speed. The HSI16 frequency can be trimmed in the application using the HSITRIM[6:0] bits in the RCC internal clock sources calibration register (RCC_ICSCR).
Page 239 RM0461 Reset and clock control (RCC) Software calibration The MSI RC oscillator frequency can vary from one chip to another due to manufacturing process variations. This is why each device is factory calibrated by ST for 1 % accuracy at an ambient temperature T = 25 °C.
Page 240: Figure 24. Lse Clock Sources
Reset and clock control (RCC) RM0461 Figure 24. LSE clock sources Clock source Hardware configuration OSC32_IN OSC32_OUT Crystal/ ceramic resonators Load capacitors OSC32_OUT OSC32_IN External GPIO External clock source MSv62608V1 The LSE crystal is switched on and off using the LSEON bit in the RCC Backup domain control register (RCC_BDCR).
Page 241: Table 49. Clock Source Stabilization Times
RM0461 Reset and clock control (RCC) The LSI RC can be switched on and off using the LSION bit in the RCC control/status register (RCC_CSR). The LSIRDY flag in the RCC control/status register (RCC_CSR) indicates if the LSI oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock interrupt enable register (RCC_CIER).
Page 242: Table 50. Clock Source Frequency
Reset and clock control (RCC) RM0461 6.2.9 Clock source frequency versus voltage scaling The following table gives the different clock source frequencies depending on the product voltage range. Table 50. Clock source frequency Clock frequency Product voltage range HSI16 HSE32 PLLRCLK = PLLQCLK = 48 MHz Range 1 48 MHz...
Page 243: Table 51. Spi2S2 I2S Clock Pll Configurations
RM0461 Reset and clock control (RCC) The CSS on LSE is working in all modes except VBAT. It is working also under system reset (excluding power on reset). If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied to the RTC but no hardware action is made to the registers.
Page 244 Reset and clock control (RCC) RM0461 6.2.14 ADC clock The ADC clock is derived from the system clock, from the HSI16 clock, or from the PLL output. The ADC clock can reach 35 MHz and can be divided by the following prescalers values: 1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128 or 256 by configuring the ADC_CCR register.
Page 245 RM0461 Reset and clock control (RCC) 6.2.18 True RNG clock The true random number generator (RNG) seed clock is derived from the MSI, from the PLL output or from the LSE or LSI clock. It can reach 48 MHz and can be divided by a prescalers values by configuring the true RNG register.
Page 246: Figure 25. Frequency Measurement With Tim16 In Capture Mode
Reset and clock control (RCC) RM0461 6.2.20 Internal/external clock measurement with TIM16/TIM17 The frequency of all on-board clock sources can be indirectly measured by mean of the TIM16 or TIM17 channel 1 input capture, as shown in Figure 25 Figure Figure 25.
Page 247 RM0461 Reset and clock control (RCC) The TIM17 input capture channel can be a GPIO line or an internal clock of the MCU. This selection is performed through the TI1_RMP[1:0] bits in the TIM17_OR register. The possibilities are listed below: •...
Page 248: Table 53. Peripheral Clock Enable
Reset and clock control (RCC) RM0461 6.2.21 Peripheral clocks enable Most peripheral bus and kernel clocks can be individually enabled.The RCC_AHBxENR and RCC_APBxENRy registers enable peripheral clocks. The peripheral clocks follow the CPU state and the system state (see the table below). The RTC kernel clock is enabled by the RTCEN bit and does not depend on the CPU state nor the system state.
Page 249: Table 54. Low-Power Debug Configurations
RM0461 Reset and clock control (RCC) by the peripheral (USART1, USART2, LPUART1, I2C1, I2C2 or I2C3) that allows the wakeup from Stop modes. All U(S)ARTs, LPUARTs and I2Cs have the capability to enable the HSI16 oscillator even when the MCU is in Stop mode (if HSI16 is selected as clock source for that peripheral). All U(S)ARTs, LPUARTs and LPTIMs can also be driven by the LSE oscillator when the system is in Stop mode (if LSE is selected as clock source for that peripheral) and the LSE oscillator is enabled (LSEON).
Page 250 Reset and clock control (RCC) RM0461 domain is ongoing, Stop, Standby and Shutdown modes entry is delayed until the APB access is finished. RCC registers 6.4.1 RCC clock control register (RCC_CR) Address offset: 0x000 Reset value: 0x0000 0061 Access: no wait state, word, half-word and byte access HSEBY Res.
Page 251 RM0461 Reset and clock control (RCC) Bit 19 CSSON: HSE32 clock security system enable This bit is set by software to enable the clock security system. When CSSON is set, the HSE32 lock detector is enabled by hardware when the HSE32 oscillator is ready, and disabled by hardware if a HSE32 clock failure is detected.
Page 252 Reset and clock control (RCC) RM0461 Bit 9 HSIKERON: HSI16 enable for peripheral kernel clocks This bit is set and cleared by software to force HSI16 on even in Stop modes. HSI16 enabled by HSIKERON can only feed USARTs, LPUARTs and I2Cs peripherals configured with HSI16 as kernel clock.
Page 253 RM0461 Reset and clock control (RCC) Bit 1 MSIRDY: MSI clock ready flag This bit is set and cleared by hardware to indicate that the MSI oscillator is stable or not. After reset, this bit is read 1 once the MSI is ready. 0: MSI oscillator not ready 1: MSI oscillator ready Note: Once MSION is cleared, MSIRDY goes low after six MSI clock cycles.
Page 254 Reset and clock control (RCC) RM0461 Bits 7:0 MSICAL[7:0]: MSI clock calibration These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value.
Page 255 RM0461 Reset and clock control (RCC) Bits 27:24 MCOSEL[3:0]: Microcontroller clock output selection These bits are set and cleared by software. 0000: MCO output disabled, no clock on MCO 0001: SYSCLK system clock selected 0010: MSI clock selected. 0011: HSI16 clock selected. 0100: HSE32 clock selected (after stabilization) 0101: Main PLLRCLK clock selected 0110: LSI clock selected...
Page 256 Reset and clock control (RCC) RM0461 Bits 13:11 PPRE2[2:0]: PCLK2 high-speed prescaler (APB2) These bits are set and cleared by software to control the division factor of the PCLK2 clock (APB2). The PPRE2F flag can be checked to know if the programmed PPRE2 prescaler value is applied.
Page 257 RM0461 Reset and clock control (RCC) Bits 1:0 SW[1:0]: System clock switch These bits are set and cleared by software to select system clock source (SYSCLK). They are configured by hardware to force MSI oscillator selection when exiting Shutdown mode and Standby mode.
Page 258 Reset and clock control (RCC) RM0461 Bit 28 PLLREN: Main PLL PLLRCLK output enable This bit is set and reset by software to enable the PLLRCLK output of the main PLL. It cannot be written when PLLRCLK output of the PLL is used as system clock. In order to save power, when the PLLRCLK output of the PLL is not used, the value of PLLREN must be 0.
Page 259 RM0461 Reset and clock control (RCC) Bit 16 PLLPEN: Main PLL PLLPCLK output enable This bit is set and reset by software to enable the PLLPCLK output of the main PLL. In order to save power, when the PLLPCLK output of the PLL is not used, the value of PLLPEN must be 0.
Page 260 Reset and clock control (RCC) RM0461 6.4.5 RCC clock interrupt enable register (RCC_CIER) Address offset: 0x018 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 261 RM0461 Reset and clock control (RCC) Bit 2 MSIRDYIE: MSI ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization. 0: MSI ready interrupt disabled 1: MSI ready interrupt enabled Bit 1 LSERDYIE: LSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.
Page 262 Reset and clock control (RCC) RM0461 Bit 4 HSERDYF: HSE32 ready interrupt flag This bit is set by hardware when the HSE32 clock becomes stable and HSERDYDIE is set. It is cleared by software setting the HSERDYC bit. 0: No clock ready interrupt caused by the HSE32 oscillator 1: Clock ready interrupt caused by the HSE32 oscillator Bit 3 HSIRDYF: HSI16 ready interrupt flag This bit is set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in...
Page 263 RM0461 Reset and clock control (RCC) Bits 31:10 Reserved, must be kept at reset value. Bit 9 LSECSSC: LSE CSS flag clear This bit is set by software to clear the LSECSSF flag. 0: No effect 1: LSECSSF flag cleared Bit 8 CSSC: HSE32 CSS flag clear This bit is set by software to clear the HSE32 CSSF flag.
Page 264 Reset and clock control (RCC) RM0461 6.4.8 RCC AHB1 peripheral reset register (RCC_AHB1RSTR) Address offset: 0x028 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 265 RM0461 Reset and clock control (RCC) Bits 31:8 Reserved, must be kept at reset value. Bit 7 GPIOHRST: IO port H reset This bit is set and cleared by software. 0: No effect 1: IO port H reset Bits 6:3 Reserved, must be kept at reset value. Bit 2 GPIOCRST: IO port C reset This bit is set and cleared by software.
Page 266 Reset and clock control (RCC) RM0461 Bit 18 RNGRST: True RNG reset This bit is set and cleared by software. 0: No effect 1: True RNG reset Bit 17 AESRST: AES hardware accelerator reset This bit is set and cleared by software. 0: No effect 1: AES reset Bit 16 PKARST: PKA hardware accelerator reset...
Page 267 RM0461 Reset and clock control (RCC) Bit 22 I2C2RST: I2C2 reset This bit is set and cleared by software. 0: No effect 1: I2C2 reset Bit 21 I2C1RST: I2C1 reset This bit is set and cleared by software. 0: No effect 1: I2C1 reset Bits 20:18 Reserved, must be kept at reset value.
Page 268 Reset and clock control (RCC) RM0461 Bits 31:7 Reserved, must be kept at reset value. Bit 6 LPTIM3RST: Low-power timer 3 reset This bit is set and cleared by software. 0: No effect 1: LPTIM3 reset Bit 5 LPTIM2RST: Low-power timer 2 reset This bit is set and cleared by software.
Page 269 RM0461 Reset and clock control (RCC) Bit 12 SPI1RST: SPI1 reset This bit is set and cleared by software. 0: No effect 1: SPI1 reset Bit 11 TIM1RST: Timer 1 reset This bit is set and cleared by software. 0: No effect 1: TIM1 reset Bit 10 Reserved, must be kept at reset value.
Page 270 Reset and clock control (RCC) RM0461 6.4.15 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) Address offset: 0x048 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.
Page 271 RM0461 Reset and clock control (RCC) 6.4.16 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) Address offset: 0x04C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.
Page 272 Reset and clock control (RCC) RM0461 6.4.17 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) Address offset: 0x050 Reset value: 0x0208 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.
Page 273 RM0461 Reset and clock control (RCC) 6.4.18 RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) Address offset: 0x058 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.
Page 274 Reset and clock control (RCC) RM0461 Bit 14 SPI2S2EN: SPI2S2 clock enable This bit is set and cleared by software. 0: SPI2S2 clock disabled 1: SPI2S2 clock enabled Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGEN: Window watchdog clock enable This bit is set by software to enable the window watchdog clock.
Page 275 RM0461 Reset and clock control (RCC) Bits 31:7 Reserved, must be kept at reset value. Bit 6 LPTIM3EN: Low-power timer 3 clocks enable This bit is set and cleared by software. 0: LPTIM3 bus and kernel clocks disabled 1: LPTIM3 bus and kernel clocks enable Bit 5 LPTIM2EN: Low-power timer 2 clocks enable Set and cleared by software.
Page 276 Reset and clock control (RCC) RM0461 Bit 13 Reserved, must be kept at reset value. Bit 12 SPI1EN: SPI1 clock enable This bit is set and cleared by software. 0: SPI1 clock disabled 1: SPI1 clock enabled Bit 11 TIM1EN: TIM1 timer clock enable This bit is set and cleared by software.
Page 277 RM0461 Reset and clock control (RCC) 6.4.22 RCC AHB1 peripheral clock enable in Sleep mode register (RCC_AHB1SMENR) Address offset: 0x068 Reset value: 0x0000 1007 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res.
Page 278 Reset and clock control (RCC) RM0461 6.4.23 RCC AHB2 peripheral clock enable in Sleep mode register (RCC_AHB2SMENR) Address offset: 0x06C Reset value: 0x0000 0087 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res.
Page 279 RM0461 Reset and clock control (RCC) 6.4.24 RCC AHB3 peripheral clock enable in Sleep and Stop mode register (RCC_AHB3SMENR) Address offset: 0x070 Reset value: 0x0387 0000 Access: no wait state, word, half-word and byte access FLASH SRAM2 SRAM1 Res. Res. Res.
Page 280 Reset and clock control (RCC) RM0461 6.4.25 RCC APB1 peripheral clock enable in Sleep mode register 1 (RCC_APB1SMENR1) Address offset: 0x078 Reset value: 0xA0E2 4C01 Access: no wait state, word, half-word and byte access LPTIM1 I2C3 I2C2 I2C1 USART2 Res. Res.
Page 281 RM0461 Reset and clock control (RCC) Bit 17 USART2SMEN: USART2 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0: USART2 bus clock disabled by the clock gating during Sleep and Stop modes 1: USART2 bus clock enabled by the clock gating during Sleep mode, disabled during Stop mode Bits 16:15 Reserved, must be kept at reset value.
Page 282 Reset and clock control (RCC) RM0461 Bits 31:7 Reserved, must be kept at reset value. Bit 6 LPTIM3SMEN: Low-power timer 3 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0: LPTIM3 bus clock disabled by the clock gating during Sleep and Stop modes 1: LPTIM3 bus clock enabled by the clock gating during Sleep mode, disabled during Stop mode Bit 5 LPTIM2SMEN: Low power timer 2 clock enable during Sleep and Stop modes...
Page 283 RM0461 Reset and clock control (RCC) Bit 14 USART1SMEN: USART1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0: USART1 bus clock disabled by the clock gating during Sleep and Stop modes 1: USART1 bus clock enabled by the clock gating during Sleep mode, disabled during Stop mode Bit 13 Reserved, must be kept at reset value.
Page 284 Reset and clock control (RCC) RM0461 6.4.29 RCC peripherals independent clock configuration register (RCC_CCIPR) Address offset: 0x088 Reset value: 0x0000 0000 Access: no wait states, word, half-word and byte access RNGSEL[1:0] ADCSEL[1:0] Res. Res. Res. Res. LPTIM3SEL[1:0] LPTIM2SEL[1:0] LPTIM1SEL[1:0] I2C3SEL[1:0] LPUART1SEL SPI2S2SEL USART2SEL...
Page 285 RM0461 Reset and clock control (RCC) Bits 17:16 I2C3SEL[1:0]: I2C3 clock source selection These bits are set and cleared by software to select the I2C3 clock source. 00: PCLK selected 01: System clock (SYSCLK) selected 10: HSI16 clock selected 11: Reserved Bits 15:14 I2C2SEL[1:0]: I2C2 clock source selection These bits are set and cleared by software to select the I2C2 clock source.
Page 286 Reset and clock control (RCC) RM0461 6.4.30 RCC Backup domain control register (RCC_BDCR) Address offset: 0x090 Reset value: 0x0000 0000 Reset by Backup domain reset, except LSCOSEL, LSCOEN and BDRST that are reset only by Backup domain power-on reset but not reset by wakeup from Standby and NRST pad. Access: 0 ≤...
Page 287 RM0461 Reset and clock control (RCC) Bit 11 LSESYSRDY: LSE system clock ready This bit is set and cleared by hardware to indicate when the LSE system clock is ready after the LSESYSEN bit is set. This bit is only valid when LSEON, LSERDY and LSESYSEN are set.
Page 288 Reset and clock control (RCC) RM0461 Bit 2 LSEBYP: LSE oscillator bypass This bit is set and cleared by software to bypass the LSE oscillator. It can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: LSE oscillator ready...
Page 289 RM0461 Reset and clock control (RCC) Bit 31 LPWRRSTF: Low-power reset flag This bit is set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown mode entry. It is cleared by writing to the RMVF bit. 0: No illegal mode reset occurred 1: Illegal mode reset occurred Bit 30 WWDGRSTF: Window watchdog reset flag...
Page 290 Reset and clock control (RCC) RM0461 Bit 15 RFRST: Sub-GHz radio reset This bit is set and cleared by software. 0: Sub-GHz radio software reset removed 1: Sub-GHz radio software reset active Bit 14 RFRSTF: Sub-GHz radio in reset status flag This bit is set and cleared by hardware.
Page 291 RM0461 Reset and clock control (RCC) 6.4.32 RCC extended clock recovery register (RCC_EXTCFGR) Address offset: 0x108 Reset value: 0x0003 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 292: Table 55. Rcc Register Map And Reset Values
Reset and clock control (RCC) RM0461 6.4.33 RCC register map Table 55. RCC register map and reset values Register Offset name RCC_CR 0x000 Reset value HSITRIM[6:0] HSICAL[7:0] MSITRIM[7:0] MSICAL[7:0] RCC_ICSCR 0x004 Reset value PPRE2[ PPRE1 HPRE[3:0] RCC_CFGR 2:0] [2:0] [1:0] [1:0] 0x008 Reset value...
Page 293 RM0461 Reset and clock control (RCC) Table 55. RCC register map and reset values (continued) Register Offset name RCC_ AHB3RSTR 0x030 Reset value Reserved 0x034 Reserved RCC_ APB1RSTR1 0x038 Reset value RCC_ APB1RSTR2 0x03C Reset value RCC_ APB2RSTR 0x040 Reset value RCC_ APB3RSTR 0x044...
Page 294 Reset and clock control (RCC) RM0461 Table 55. RCC register map and reset values (continued) Register Offset name RCC_ APB1ENR2 0x05C Reset value RCC_ APB2ENR 0x060 Reset value RCC_ APB3ENR 0x064 Reset value RCC_ AHB1SMENR 0x068 Reset value RCC_ AHB2SMENR 0x06C Reset value RCC_...
Page 295 RM0461 Reset and clock control (RCC) Table 55. RCC register map and reset values (continued) Register Offset name RCC_APB2 SMENR 0x080 Reset value RCC_ APB3SMENR 0x084 Reset value RCC_CCIPR 0x088 Reset value Reserved 0x08C Reserved RCC_BDCR 0x090 Reset value RCC_CSR 0x094 Reset value 0x098-...
Page 296 Hardware semaphore (HSEM) RM0461 Hardware semaphore (HSEM) Introduction The hardware semaphore block provides 16 (32-bit) register based semaphores. The semaphores can be used to ensure synchronization between different processes running on the core. The HSEM provides a non-blocking mechanism to lock semaphores in an atomic way.
Page 297: Table 56. Hsem Internal Input/Output Signals
RM0461 Hardware semaphore (HSEM) Functional description 7.3.1 HSEM block diagram As shown in Figure 27, the HSEM is based on three sub-blocks: • the semaphore block containing the semaphore status and IDs • the semaphore interface block providing AHB access to the semaphore via the HSEM_Rx and HSEM_RLRx registers •...
Page 298: Figure 28. Procedure State Diagram
Hardware semaphore (HSEM) RM0461 The semaphore is free when its LOCK bit is 0. In this case, the MASTERID and PROCID are also 0. When the LOCK bit is 1, the semaphore is locked and the MASTERID indicates which AHB bus master ID has locked it. The PROCID indicates which process of that AHB bus master ID has locked the semaphore.
Page 299 RM0461 Hardware semaphore (HSEM) 1-step (read) lock procedure The 1-step procedure consists in a read to lock and check the semaphore in a single step, carried out from the HSEM_RLRx register. • Read lock semaphore with the AHB bus master MASTERID. •...
Page 300 Hardware semaphore (HSEM) RM0461 7.3.6 HSEM MASTERID semaphore clear All semaphores locked by a MASTERID can be unlocked at once by using the HSEM_CR register. Write MASTERID and correct KEY value in HSEM_CR. All locked semaphores with a matching MASTERID are unlocked, and may generate an interrupt when enabled. An interrupt may be generated for the unlocked semaphore(s).
Page 301: Figure 29. Interrupt State Diagram
RM0461 Hardware semaphore (HSEM) Figure 29. Interrupt state diagram Semaphore x locked WRITE (MASTERID & PROCID & LOCK = 0) Interrupt Semaphore x Status = 1 Interrupt Semaphore x Enabled Interrupt Semaphore x MaskedStatus = 1 & Interrupt x generated Semaphore x free MSv41951V3 The procedure to get an interrupt when a semaphore becomes free is described hereafter.
Page 302: Table 57. Authorized Ahb Bus Master Id
Hardware semaphore (HSEM) RM0461 – If the semaphore lock fails, wait for semaphore free interrupt. Note: An interrupt does not lock the semaphore. After an interrupt, either the AHB bus master or the process must still perform the lock procedure to lock the semaphore. 7.3.8 AHB bus master ID verification The HSEM allows only authorized AHB bus master ID to lock and unlock semaphores.
Page 303 RM0461 Hardware semaphore (HSEM) HSEM registers Registers must be accessed using word format. Byte and half-word accesses are ignored and have no effect on the semaphores, they generate a bus error. 7.4.1 HSEM register semaphore x (HSEM_Rx) Address offset: 0x000 + 0x4 * x (x = 0 to 15) Reset value: 0x0000 0000 The HSEM_Rx must be used to perform a 2-step write lock, read back, and for unlocking a semaphore.
Page 304 Hardware semaphore (HSEM) RM0461 7.4.2 HSEM read lock register semaphore x (HSEM_RLRx) Address offset: 0x080 + 0x4 * x (x = 0 to 15) Reset value: 0x0000 0000 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx must be used to perform a 1-step read lock.
Page 305 RM0461 Hardware semaphore (HSEM) 7.4.3 HSEM interrupt enable register (HSEM_IER) Address offset: 0x100 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ISE[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 ISE[15:0]: Interrupt semaphore x enable bit (x = 0 to 15) This bit is read and written by software.
Page 306 Hardware semaphore (HSEM) RM0461 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 ISF[15:0]: Interrupt semaphore x status bit before enable (mask) (x = 0 to 15) This bit is set by hardware, and reset only by software. This bit is cleared by software writing the corresponding HSEM_ICR bit.
Page 307 RM0461 Hardware semaphore (HSEM) Bits 15:13 Reserved, must be kept at reset value. Bit 12 Reserved, must be kept at reset value. Bits 11:8 MASTERID[3:0]: MASTERID of semaphores to be cleared This field can be written by software and is always read 0. This field indicates the MASTERID for which the semaphores are cleared when writing the HSEM_CR.
Page 308: Table 58. Hsem Register Map And Reset Values
Hardware semaphore (HSEM) RM0461 7.4.9 HSEM register map Table 58. HSEM register map and reset values Offset Register name MASTERID HSEM_R0 PROCID[7:0] 0x000 [3:0] Reset value MASTERID HSEM_R1 PROCID[7:0] [3:0] 0x004 Reset value MASTERID HSEM_R15 PROCID[7:0] [3:0] 0x03C Reset value MASTERID HSEM_RLR0 PROCID...
Page 309 RM0461 General-purpose I/Os (GPIO) General-purpose I/Os (GPIO) GPIO introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR) and one 32-bit set/reset register (GPIOx_BSRR). All GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).
Page 310: Figure 30. Basic Structure Of A Standard I/O Port Bit
General-purpose I/Os (GPIO) RM0461 GPIOx_BSRR and GPIOx_BRR registers allow atomic read/modify accesses to any of the GPIOx_ODR registers. In this way, there is no risk of an IRQ occurring between the read and the modify access. Figure 30 Figure 31 show the basic structure of a standard and a 5V-tolerant I/O port bit.
Page 311: Table 59. Port Bit Configurations
RM0461 General-purpose I/Os (GPIO) Figure 31. Basic structure of a 5V-tolerant I/O port bit To on-chip peripheral Alternate function input on/off Read DD_FT DDIOx TTL Schmitt Protection trigger on/off diode Pull Input driver I/O pin Write Output driver on/off DDIOx Protection Pull down...
Page 312 General-purpose I/Os (GPIO) RM0461 Table 59. Port bit configurations (continued) MODE(i)[1:0] OTYPER(i) OSPEED(i)[1:0] PUPD(i)[1:0] I/O configuration Input Floating Input Input Reserved (input floating) Input/output Analog Reserved 1. GP = general purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open drain, AF = alternate function. 8.3.1 General purpose I/O (GPIO) During and just after reset, the alternate functions are not active and most of the I/O ports...
Page 313 RM0461 General-purpose I/Os (GPIO) Specific alternate function assignments for each pin are detailed in the product datasheet. In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped on different I/O pins to optimize the number of peripherals available in smaller packages.
Page 314 General-purpose I/Os (GPIO) RM0461 To each bit in GPIOx_ODR correspond two control bits in GPIOx_BSRR, BS(i) and BR(i): • When written to 1, BS(i) sets the corresponding ODR(i) bit. • When written to 1, BR(i) resets the ODR(i) corresponding bit. Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in GPIOx_ODR.
Page 315: Figure 32. Input Floating/Pull-Up/Pull-Down Configurations
RM0461 General-purpose I/Os (GPIO) 8.3.9 Input configuration When the I/O port is programmed as input, the following occurs: • The output buffer is disabled. • The Schmitt trigger input is activated. • The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register.
Page 316: Figure 33. Output Configuration
General-purpose I/Os (GPIO) RM0461 The figure below shows the output configuration of the I/O port bit. Figure 33. Output configuration Read DDIOx TTL Schmitt DDIOx trigger on/off protection Write diode Input driver pull I/O pin Output driver DDIOx on/off P-MOS protection pull Output...
Page 317: Figure 35. High Impedance Analog Configuration
RM0461 General-purpose I/Os (GPIO) 8.3.12 Analog configuration When the I/O port is programmed as analog configuration, the following occurs: • The output buffer is disabled. • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0). •...
Page 318 General-purpose I/Os (GPIO) RM0461 8.3.15 Using PH3 as GPIO PH3 may be used as boot pin (BOOT0) or as GPIO. PH3 switches from the input mode to the analog input mode depending on the nSWBOOT0 bit in the user option byte as follows: •...
Page 319 RM0461 General-purpose I/Os (GPIO) 8.4.2 GPIOx output type register (GPIOx_OTYPER) (x = A to B) Address offset: Block A: 0x0004 Address offset: Block B: 0x0404 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 320 General-purpose I/Os (GPIO) RM0461 8.4.4 GPIOx pull-up/pull-down register (GPIOx_PUPDR) (x = A to B) Address offset: Block A: 0x000C Address offset: Block B: 0x040C Reset value: Block A: 0x6400 0000 Reset value: Block B: 0x0000 0100 PUPD15[1:0] PUPD14[1:0] PUPD13[1:0] PUPD12[1:0] PUPD11[1:0] PUPD10[1:0] PUPD9[1:0]...
Page 321 RM0461 General-purpose I/Os (GPIO) 8.4.6 GPIOx output data register (GPIOx_ODR) (x = A to B) Address offset: Block A: 0x0014 Address offset: Block B: 0x0414 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 322 General-purpose I/Os (GPIO) RM0461 8.4.8 GPIOx configuration lock register (GPIOx_LCKR) (x = A to B) Address offset: Block A: 0x001C Address offset: Block B: 0x041C Reset value: 0x0000 0000 This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK).
Page 323 RM0461 General-purpose I/Os (GPIO) 8.4.9 GPIOx alternate function low register (GPIOx_AFRL) (x = A to B) Address offset: Block A: 0x0020 Address offset: Block B: 0x0420 Reset value: 0x0000 0000 AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0] Bits 31:0 AFSELy[3:0]: Port Pxy alternate function selection (y = 7 to 0) These bits are written by software to configure alternate function I/Os 0x0: AF0 selected 0x1: AF1 selected...
Page 324 General-purpose I/Os (GPIO) RM0461 8.4.11 GPIOx bit reset register (GPIOx_BRR) (x = A to B) Address offset: Block A: 0x0028 Address offset: Block B: 0x0428 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 325 RM0461 General-purpose I/Os (GPIO) Bits 5:4 MODE2[1:0]: Port PC2 IO type configuration Bits 3:2 MODE1[1:0]: Port PC1 IO type configuration Bits 1:0 MODE0[1:0]: Port PC0 IO type configuration These bits are written by software to configure the I/O mode. 00: Input mode 01: General purpose output mode 10: Alternate function mode 11: Analog mode (reset state)
Page 326 General-purpose I/Os (GPIO) RM0461 Bits 13:12 OSPEED6[1:0]: Port PC6 output speed configuration Bits 11:10 OSPEED5[1:0]: Port PC5 output speed configuration Bits 9:8 OSPEED4[1:0]: Port PC4 output speed configuration Bits 7:6 OSPEED3[1:0]: Port PC3 output speed configuration Bits 5:4 OSPEED2[1:0]: Port PC2 output speed configuration Bits 3:2 OSPEED1[1:0]: Port PC1 output speed configuration Bits 1:0 OSPEED0[1:0]: Port PC0 output speed configuration These bits are written by software to configure the I/O output speed.
Page 327 RM0461 General-purpose I/Os (GPIO) 8.4.16 GPIOC input data register (GPIOC_IDR) Address offset: 0x0810 Reset value: 0x0000 XXXX Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ID15 ID14 ID13 Res. Res. Res. Res. Res.
Page 328 General-purpose I/Os (GPIO) RM0461 8.4.18 GPIOC bit set/reset register (GPIOC_BSRR) Address offset: 0x0818 Reset value: 0x0000 0000 BR15 BR14 BR13 Res. Res. Res. Res. Res. Res. rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 BS15 BS14 BS13 Res. Res.
Page 329 RM0461 General-purpose I/Os (GPIO) 8.4.19 GPIOC configuration lock register (GPIOC_LCKR) Address offset: 0x081C Reset value: 0x0000 0000 This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO.
Page 330 General-purpose I/Os (GPIO) RM0461 8.4.20 GPIOC alternate function low register (GPIOC_AFRL) Address offset: 0x0820 Reset value: 0x0000 0000 Res. Res. Res. Res. AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 AFSEL6[3:0]: Port PC6 alternate function selection Bits 23:20 AFSEL5[3:0]: Port PC5 alternate function selection Bits 19:16 AFSEL4[3:0]: Port PC4 alternate function selection Bits 15:12 AFSEL3[3:0]: Port PC3 alternate function selection...
Page 331 RM0461 General-purpose I/Os (GPIO) Bits 23:20 AFSEL13[3:0]: Port PC13 alternate function selection These bits are written by software to configure alternate function I/Os. 0x0: AF0 selected 0x1: AF1 selected 0x2: AF2 selected 0xE: AF14 selected 0xF: AF15 selected Bits 19:0 Reserved, must be kept at reset value. 8.4.22 GPIOC bit reset register (GPIOC_BRR) Address offset: 0x0828...
Page 332 General-purpose I/Os (GPIO) RM0461 Bits 7:6 MODE3[1:0]: Port PH3 IO type configuration These bits are written by software to configure the I/O mode. 00: Input mode 01: General purpose output mode 10: Alternate function mode 11: Analog mode (reset state) Bits 5:0 Reserved, must be kept at reset value.
Page 333 RM0461 General-purpose I/Os (GPIO) Bits 7:6 OSPEED3[1:0]: Port PH3 output speed configuration These bits are written by software to configure the I/O output speed. 00: Low speed 01: Medium speed 10: Fast speed 11: High speed Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.
Page 334 General-purpose I/Os (GPIO) RM0461 8.4.28 GPIOH output data register (GPIOH_ODR) Address offset: 0x1C14 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 335 RM0461 General-purpose I/Os (GPIO) 8.4.30 GPIOH configuration lock register (GPIOH_LCKR) Address offset: 0x1C1C Reset value: 0x0000 0000 This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO.
Page 336 General-purpose I/Os (GPIO) RM0461 8.4.31 GPIOH alternate function low register (GPIOH_AFRL) Address offset: 0x1C20 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AFSEL3[3:0] Res. Res. Res. Res. Res. Res.
Page 337: Table 60. Gpioa Register Map And Reset Values
RM0461 General-purpose I/Os (GPIO) 8.4.33 GPIOA register map Table 60. GPIOA register map and reset values Offset Register name GPIOA_MODER 0x0000 Reset value GPIOA_OTYPER 0x0004 Reset value GPIOA_OSPEEDR 0x0008 Reset value GPIOA_PUPDR 0x000C Reset value GPIOA_IDR 0x0010 Reset value GPIOA_ODR 0x0014 Reset value GPIOA_BSRR...
Page 338: Table 61. Gpiob Register Map And Reset Values
General-purpose I/Os (GPIO) RM0461 8.4.34 GPIOB register map Table 61. GPIOB register map and reset values Offset Register name GPIOB_MODER 0x0400 Reset value GPIOB_OTYPER 0x0404 Reset value GPIOB_OSPEEDR 0x0408 Reset value GPIOB_PUPDR 0x040C Reset value GPIOB_IDR 0x0410 Reset value GPIOB_ODR 0x0414 Reset value GPIOB_BSRR...
Page 339: Table 62. Gpioc Register Map And Reset Values
RM0461 General-purpose I/Os (GPIO) 8.4.35 GPIOC register map Table 62. GPIOC register map and reset values Offset Register name GPIOC_MODER 0x0800 Reset value GPIOC_OTYPER 0x0804 Reset value GPIOC_OSPEEDR 0x0808 Reset value GPIOC_PUPDR 0x080C Reset value GPIOC_IDR 0x0810 Reset value GPIOC_ODR 0x0814 Reset value GPIOC_BSRR...
Page 340: Table 63. Gpioh Register Map And Reset Values
General-purpose I/Os (GPIO) RM0461 8.4.36 GPIOH register map Table 63. GPIOH register map and reset values Offset Register name GPIOH_MODER 0x1C00 Reset value GPIOH_OTYPER 0x1C04 Reset value GPIOH_OSPEEDR 0x1C08 Reset value GPIOH_PUPDR 0x1C0C Reset value GPIOH_IDR 0x1C10 Reset value GPIOH_ODR 0x1C14 Reset value GPIOH_BSRR...
Page 341 RM0461 System configuration controller (SYSCFG) System configuration controller (SYSCFG) SYSCFG main features STM32WLEx devices feature a set of configuration registers. The main purposes of the system configuration controller are the following: • Remapping memory areas • Managing the external interrupt line connection to the GPIOs •...
Page 342 System configuration controller (SYSCFG) RM0461 9.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1) Address offset: 0x004 Reset value: 0x7C00 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 343 RM0461 System configuration controller (SYSCFG) Bit 8 BOOSTEN: I/O analog switch voltage booster enable 0: I/O analog switches are supplied by V voltage. This is the recommended configuration when using the ADC in high V voltage operation. 1: I/O analog switches are supplied by a dedicated voltage booster (supplied by V ).
Page 344 System configuration controller (SYSCFG) RM0461 Bits 2:0 EXTI0[2:0]: EXTI0 configuration bits These bits are written by software to select the source input for the EXTI0 external interrupt. 000: PA0 pin 001: PB0 pin 010: PC0 pin Others: Reserved Note: Some of the I/O pins mentioned in this register may not be available on small packages. 9.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)
Page 345 RM0461 System configuration controller (SYSCFG) Bits 2:0 EXTI4[2:0]: EXTI4 configuration bits These bits are written by software to select the source input for the EXTI4 external interrupt. 000: PA4 pin 001: PB4 pin 010: PC4 pin Others: Reserved Note: Some of the I/O pins mentioned in this register may not be available on small packages. 9.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)
Page 346 System configuration controller (SYSCFG) RM0461 Note: Some of the I/O pins mentioned in this register may not be available on small packages. 9.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x014 Reset value: 0x0000 0000 Res. Res. Res. Res.
Page 347 RM0461 System configuration controller (SYSCFG) 9.2.7 SYSCFG SRAM control and status register (SYSCFG_SCSR) Address offset: 0x18 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PKASR SRAM SRAM2 Res. Res.
Page 348 System configuration controller (SYSCFG) RM0461 Bits 7:4 Reserved, must be kept at reset value. Bit 3 ECCL: ECC lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Flash ECC error connection to TIM1/16/17 break input. 0: ECC error disconnected from TIM1/16/17 break input.
Page 349: Table 64. Syscfg Register Map And Reset Values
RM0461 System configuration controller (SYSCFG) 9.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR) Address offset: 0x024 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 350 System configuration controller (SYSCFG) RM0461 Table 64. SYSCFG register map and reset values (continued) Offset Register name SYSCFG_CFGR1 0x004 Reset value EXTI3 EXTI2 EXTI1 EXTI0 SYSCFG_EXTICR1 [2:0] [2:0] [2:0] [2:0] 0x008 Reset value EXTI7 EXTI6 EXTI5 EXTI4 SYSCFG_EXTICR2 [2:0] [2:0] [2:0] [2:0] 0x00C...
Page 351: Table 65. Stm32Wlex Peripherals Interconnect Matrix
Depending on peripherals, these interconnections can operate in Run, Sleep, LPRun, LPSleep, Stop 0, Stop 1 and Stop 2 modes. 10.2 Connection summary (1) (2) Table 65. STM32WLEx peripherals interconnect matrix Destination Source TIM1 TIM2 TIM16...
Page 352 Peripherals interconnect matrix RM0461 (1) (2) Table 65. STM32WLEx peripherals interconnect matrix (continued) Destination Source COMP1 COMP2 SYST ERR 1. Numbers in this table are links to corresponding subsections of Section 10.3: Interconnection details. The “-” symbol in grayed cells means no interconnect.
Page 353 RM0461 Peripherals interconnect matrix 10.3.2 From timer (LPTIM1/LPTIM2) to timer (LPTIM3) Purpose Some timers are linked together internally for synchronization or chaining. When one timer is configured in Master mode, it can reset, start, stop or clock the counter of another timer configured in Slave mode.
Page 354 Peripherals interconnect matrix RM0461 10.3.4 From timer (LPTIM1/LPTIM2) to DAC Purpose Low-power timer LPTIM1/LPTIM2 can be used to generate an DAC trigger event. DAC triggering is described in Section 17.4.7: DAC trigger selection. Triggering signals The output from low-power timer is on signals LPTIMx_OUT event. The input to DAC is on signals dac_ch1_trg[15:0].
Page 355 RM0461 Peripherals interconnect matrix External clock LSE can be used as input to general-purpose timers (TIM2) on TIM2_ETR pin (see TIM2 option register 1 (TIM2_OR1)). Active power modes Run, Sleep, LPRun, LPSleep 10.3.7 From RTC, TAMP, COMP1, COMP2 to low-power timers (LPTIM1/LPTIM2) Purpose RTC alarm A/B, TAMP_IN1/2/3 input detection and COMP1/2_OUT can be used as trigger...
Page 356 Peripherals interconnect matrix RM0461 10.3.9 From internal analog to ADC Purpose Internal temperature sensor (V ), Internal reference voltage (V ) and V monitoring REFINT channel are connected to ADC input channel. This is according to the following sections: • Section 16.2: ADC main features •...
Page 357 RM0461 Peripherals interconnect matrix 10.3.11 From system errors to timers (TIM1/TIM16/TIM17) Purpose CSS, CPU hard fault, RAM parity error, FLASH ECC double error detection and PVD can generate system errors in the form of timer break toward timers (TIM1/TIM16/TIM17). The purpose of the break function is to protect power switches driven by PWM signals generated by the timers.
Page 358 Peripherals interconnect matrix RM0461 10.3.14 From timer (LPTIM3) to sub-GHz radio SPI NSS Purpose Low-power timer LPTIM3 can be used to generate a sub-GHz radio SPI NSS event. Triggering signals The output from low-power timer is on signal LPTIM3_OUT event. The connection between timers and sub-GHz radio SPI NSS is provided in PWR sub-GHz SPI control register...
Page 359 RM0461 Direct memory access controller (DMA) Direct memory access controller (DMA) 11.1 Introduction The direct memory access (DMA) controller is a bus master and system peripheral. The DMA is used to perform programmable data transfers between memory-mapped peripherals and/or memories, upon the control of an off-loaded CPU. The DMA controller features a single AHB master architecture.
Page 360: Table 66. Dma1 And Dma2 Implementation
Direct memory access controller (DMA) RM0461 11.3 DMA implementation 11.3.1 DMA1 and DMA2 DMA1 and DMA2 are implemented with the hardware configuration parameters shown Table Table 66. DMA1 and DMA2 implementation Feature DMA1 DMA2 Number of channels 11.3.2 DMA request mapping The DMA controller is connected to DMA requests from the AHB/APB peripherals through the DMAMUX peripheral.
Page 361: Figure 36. Dma Block Diagram
RM0461 Direct memory access controller (DMA) 11.4 DMA functional description 11.4.1 DMA block diagram The DMA block diagram is shown in Figure Figure 36. DMA block diagram DMA1 Ch 1 Ch 2 AHB master interface Ch 7 dma1_req [1..7] Arbiter dma1_ack [1..7] dma1_priv[1..7] Interrupt...
Page 362: Table 67. Dma Internal Input/Output Signals
Direct memory access controller (DMA) RM0461 The DMA controller performs direct memory transfer by sharing the AHB system bus with other system masters. The bus matrix implements round-robin scheduling. DMA requests may stop the CPU access to the system bus for a number of bus cycles, when CPU and DMA target the same destination (memory or peripheral).
Page 363 RM0461 Direct memory access controller (DMA) For a given channel x, a DMA block transfer consists of a repeated sequence of: • a single DMA transfer, encapsulating two AHB transfers of a single data, over the DMA AHB bus master: –...
Page 364 Direct memory access controller (DMA) RM0461 The register that contains the amount of data items to transfer is decremented after each transfer. A DMA channel is programmed at block transfer level. Programmable data sizes The transfer sizes of a single data (byte, half-word, or word) to the peripheral and memory are programmable through, respectively, the PSIZE[1:0] and MSIZE[1:0] fields of the DMA_CCRx register.
Page 365 RM0461 Direct memory access controller (DMA) Channel configuration procedure The following sequence is needed to configure a DMA channel x: Set a channel x to privileged or unprivileged, by a privileged write access to the privileged PRIV bit of the DMA_CCRx register. Set the memory address in the DMA_CMARx register.
Page 366 Direct memory access controller (DMA) RM0461 register content may not correctly reflect the remaining data transfers versus the aborted source and destination buffer/register. • Abort and restart a channel This corresponds to the software sequence: disable an active channel, then reconfigure the channel and enable it again.
Page 367 RM0461 Direct memory access controller (DMA) Peripheral-to-peripheral mode Any DMA channel can operate in peripheral-to-peripheral mode: • when the hardware request from a peripheral is selected to trigger the DMA channel This peripheral is the DMA initiator and paces the data transfer from/to this peripheral to/from a register belonging to another memory-mapped peripheral (this one being not configured in DMA mode).
Page 368: Table 68. Programmable Data Width And Endian Behavior (When Pinc = Minc = 1)
Direct memory access controller (DMA) RM0461 11.4.6 DMA data width, alignment and endianness When PSIZE[1:0] and MSIZE[1:0] are not equal, the DMA controller performs some data alignments as described in Table Table 68. Programmable data width and endian behavior (when PINC = MINC = 1) Source Destinat Destination...
Page 369 RM0461 Direct memory access controller (DMA) Addressing AHB peripherals not supporting byte/half-word write transfers When the DMA controller initiates an AHB byte or half-word write transfer, the data are duplicated on the unused lanes of the AHB master 32-bit data bus (HWDATA[31:0]). When the AHB slave peripheral does not support byte or half-word write transfers and does not generate any error, the DMA controller writes the 32 HWDATA bits as shown in the two examples below:...
Page 370: Table 69. Dma Interrupt Requests
Direct memory access controller (DMA) RM0461 11.5 DMA interrupts An interrupt can be generated on a half transfer, transfer complete or transfer error for each DMA channel x. Separate interrupt enable bits are available for flexibility. Table 69. DMA interrupt requests Interrupt Interrupt request Interrupt event...
Page 371 RM0461 Direct memory access controller (DMA) Bit 25 TCIF7: transfer complete (TC) flag for channel 7 0: no TC event 1: a TC event occurred Bit 24 GIF7: global interrupt flag for channel 7 0: no TE, HT or TC event 1: a TE, HT or TC event occurred Bit 23 TEIF6: transfer error (TE) flag for channel 6 0: no TE event...
Page 372 Direct memory access controller (DMA) RM0461 Bit 10 HTIF3: half transfer (HT) flag for channel 3 0: no HT event 1: a HT event occurred Bit 9 TCIF3: transfer complete (TC) flag for channel 3 0: no TC event 1: a TC event occurred Bit 8 GIF3: global interrupt flag for channel 3 0: no TE, HT or TC event 1: a TE, HT or TC event occurred...
Page 373 RM0461 Direct memory access controller (DMA) 11.6.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 This register may mix privileged and unprivileged information, depending on the privileged mode of each channel (PRIV bit of the DMA_CCRx register). A privileged software is able to set any flag clear bit of the DMA_IFCR, and order DMA hardware to clear any corresponding flag(s) in the DMA_ISR register.
Page 374 Direct memory access controller (DMA) RM0461 Bit 14 CHTIF4: half transfer flag clear for channel 4 Bit 13 CTCIF4: transfer complete flag clear for channel 4 Bit 12 CGIF4: global interrupt flag clear for channel 4 Bit 11 CTEIF3: transfer error flag clear for channel 3 Bit 10 CHTIF3: half transfer flag clear for channel 3 Bit 9 CTCIF3: transfer complete flag clear for channel 3 Bit 8 CGIF3: global interrupt flag clear for channel 3...
Page 375 RM0461 Direct memory access controller (DMA) Bits 31:21 Reserved, must be kept at reset value. Bit 20 PRIV: privileged mode This bit can only be set and cleared by a privileged software. 0: disabled 1: enabled This bit must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
Page 376 Direct memory access controller (DMA) RM0461 Bits 9:8 PSIZE[1:0]: peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0.
Page 377 RM0461 Direct memory access controller (DMA) Bit 4 DIR: data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode.
Page 378 Direct memory access controller (DMA) RM0461 11.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx) Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 7) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res.
Page 379: Table 70. Dma Register Map And Reset Values
RM0461 Direct memory access controller (DMA) Bits 31:0 PA[31:0]: peripheral address It contains the base address of the peripheral data register from/to which the data is read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address.
Page 380 Direct memory access controller (DMA) RM0461 Table 70. DMA register map and reset values (continued) Offset Register DMA_IFCR 0x004 Reset value DMA_CCR1 0x008 Reset value DMA_CNDTR1 NDT[17:0] 0x00C Reset value DMA_CPAR1 PA[31:0] 0x010 Reset value DMA_CMAR1 MA[31:0] 0x014 Reset value 0x018 Reserved Reserved.
Page 381 RM0461 Direct memory access controller (DMA) Table 70. DMA register map and reset values (continued) Offset Register DMA_CCR5 0x058 Reset value DMA_CNDTR5 NDT[17:0] 0x05C Reset value DMA_CPAR5 PA[31:0] 0x060 Reset value DMA_CMAR5 MA[31:0] 0x064 Reset value 0x068 Reserved Reserved. DMA_CCR6 0x06C Reset value DMA_CNDTR6...
Page 382 DMA request multiplexer (DMAMUX) RM0461 DMA request multiplexer (DMAMUX) 12.1 Introduction A peripheral indicates a request for DMA transfer by setting its DMA request signal. The DMA request is pending until it is served by the DMA controller that generates a DMA acknowledge signal, and the corresponding DMA request signal is deasserted.
Page 383: Table 71. Dmamux Instantiation
RM0461 DMA request multiplexer (DMAMUX) 12.2 DMAMUX main features • 14-channel programmable DMA request line multiplexer output • 4-channel DMA request generator • 21 trigger inputs to DMA request generator • 21 synchronization inputs • Per DMA request generator channel: –...
Page 384: Table 72. Dmamux1: Assignment Of Multiplexer Inputs To Resources
DMA request multiplexer (DMAMUX) RM0461 Table 72. DMAMUX1: assignment of multiplexer inputs to resources request Resource request Resource request Resource MUX input MUX input MUX input dmamux_req_gen0 LPUART1_TX Reserved dmamux_req_gen1 TIM1_CH1 Reserved dmamux_req_gen2 TIM1_CH2 Reserved dmamux_req_gen3 TIM1_CH3 Reserved TIM1_CH4 Reserved DAC_OUT1 TIM1_UP Reserved...
Page 385: Table 74. Dmamux1: Assignment Of Synchronization Inputs To Resources
RM0461 DMA request multiplexer (DMAMUX) Table 73. DMAMUX1: assignment of trigger inputs to resources (continued) Trigger input Resource Trigger input Resource EXTI LINE12 Reserved EXTI LINE13 Reserved EXTI LINE14 Reserved EXTI LINE15 Reserved Table 74. DMAMUX1: assignment of synchronization inputs to resources Sync.
Page 386: Figure 37. Dmamux Block Diagram
DMA request multiplexer (DMAMUX) RM0461 12.4 DMAMUX functional description 12.4.1 DMAMUX block diagram Figure 37 shows the DMAMUX block diagram. Figure 37. DMAMUX block diagram 32-bit AHB bus dmamux_hclk DMAMUX Request multiplexer AHB slave Channel m interface DMAMUX_CmCR Channel 1 Privileged state of Channel 0 DMA requests...
Page 387: Table 75. Dmamux Signals
RM0461 DMA request multiplexer (DMAMUX) 12.4.2 DMAMUX signals Table 75 lists the DMAMUX signals. Table 75. DMAMUX signals Signal name Description dmamux_hclk DMAMUX AHB clock dmamux_req_inx DMAMUX DMA request line inputs from peripherals dmamux_trgx DMAMUX DMA request triggers inputs (to request generator sub-block) dmamux_req_genx DMAMUX request generator sub-block channels outputs DMAMUX request multiplexer sub-block inputs (from peripheral...
Page 388 DMA request multiplexer (DMAMUX) RM0461 Note: A privileged software is able to access any DMAMUX register, privileged or unprivileged. An unprivileged software is restricted to access only unprivileged DMAMUX register or register fields. When a privileged software configures a DMA channel x either as privileged, an unprivileged software is not able to access (write is ignored, read returns zero) the related DMAMUX channel registers or register fields.
Page 389: Figure 38. Synchronization Mode Of The Dmamux Request Line Multiplexer Channel
RM0461 DMA request multiplexer (DMAMUX) From this point on, each time the connected DMAMUX request is served by the DMA controller (a served request is deasserted), the DMAMUX request counter is decremented. At its underrun, the DMA request counter is automatically loaded with the value in NBREQ field of the DMAMUX_CxCR register and the input DMA request line is disconnected from the multiplexer channel x output.
Page 390: Figure 39. Event Generation Of The Dma Request Line Multiplexer Channel
DMA request multiplexer (DMAMUX) RM0461 Figure 39. Event generation of the DMA request line multiplexer channel Selected DMA request line transferred to the output DMA request pending Selected dmamux_reqx Not pending dmamux_req_outx DMA request counter dmamux_evtx DMA request counter reaches zero Event is generated on the output DMA request counter auto-reloads with NBREQ value Example with: DMAMUX_CCRx configured with: NBREQ=3, SE=0, EGE=1...
Page 391 RM0461 DMA request multiplexer (DMAMUX) 12.4.6 DMAMUX request generator The DMAMUX request generator produces DMA requests following trigger events on its DMA request trigger inputs. The DMAMUX request generator has multiple channels. DMA request trigger inputs are connected in parallel to all channels. The outputs of DMAMUX request generator channels are inputs to the DMAMUX request line multiplexer.
Page 392: Table 76. Dmamux Interrupts
DMA request multiplexer (DMAMUX) RM0461 12.5 DMAMUX interrupts An interrupt can be generated upon: • a synchronization event overrun in each DMA request line multiplexer channel • a trigger event overrun in each DMA request generator channel For each case, per-channel individual interrupt enable, status and clear flag register bits are available.
Page 393 RM0461 DMA request multiplexer (DMAMUX) 12.6 DMAMUX registers Refer to the table containing register boundary addresses for the DMAMUX base address. DMAMUX registers may be accessed per (8-bit) byte, (16-bit) half-word, or (32-bit) word. The address must be aligned with the data size. 12.6.1 DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR)
Page 394 DMA request multiplexer (DMAMUX) RM0461 Bit 8 SOIE: Synchronization overrun interrupt enable 0: Interrupt disabled 1: Interrupt enabled Bits 7:0 DMAREQ_ID[7:0]: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 12.6.2 DMAMUX request line multiplexer interrupt channel status register (DMAMUX_CSR)
Page 395 RM0461 DMA request multiplexer (DMAMUX) Bits 31:14 Reserved, must be kept at reset value. Bits 13:0 CSOF[13:0]: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. 12.6.4 DMAMUX request generator channel x configuration register (DMAMUX_RGxCR) Address offset: 0x100 + 0x04 * x (x = 0 to 3) Reset value: 0x0000 0000...
Page 396 DMA request multiplexer (DMAMUX) RM0461 12.6.5 DMAMUX request generator interrupt status register (DMAMUX_RGSR) Address offset: 0x140 Reset value: 0x0000 0000 This register shall be accessed at bit level by an unprivileged or privileged read, according to the privileged mode of the considered DMAMUX request line multiplexer channel x, depending on the privileged control bit of the connected DMA controller channel y, and considering that the DMAMUX x channel output is connected to the y channel of the DMA (refer to the DMAMXUX mapping implementation section).
Page 397 RM0461 DMA request multiplexer (DMAMUX) Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 COF[3:0]: Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. RM0461 Rev 5 397/1306...
Page 398: Table 77. Dmamux Register Map And Reset Values
DMA request multiplexer (DMAMUX) RM0461 12.6.7 DMAMUX register map The following table summarizes the DMAMUX registers and reset values. Refer to the register boundary address table for the DMAMUX register base address. Table 77. DMAMUX register map and reset values Offset Register DMAREQ_ID[6:0]...
Page 399 RM0461 DMA request multiplexer (DMAMUX) Table 77. DMAMUX register map and reset values (continued) Offset Register 0x088 - Reserved 0x0FC DMAMUX_RG0CR GNBREQ[4:0] SIG_ID[4:0] 0x100 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAMUX_RG1CR GNBREQ[4:0] SIG_ID[4:0] 0x104...
Page 400: Table 78. Vector Table
Nested vectored interrupt controller (NVIC) RM0461 Nested vectored interrupt controller (NVIC) 13.1 NVIC main features • 62 maskable interrupt channels (not including the sixteen Cortex-M4 with DSP interrupt lines) • 16 programmable priority levels (four bits of interrupt priority used) •...
Page 401 RM0461 Nested vectored interrupt controller (NVIC) Table 78. Vector table (continued) Type of Acronym Description Address priority PVD, PVD through EXTI[16] Settable 0x0000 0044 PVM[3] PVM[3] through EXTI[34] TAMP, TAMP tamper RTC_STAMP, RTC timestamp Settable 0x0000 0048 LSE_CSS, LSECSS interrupt RTC_SSRU RTC SSR underflow interrupt 3 10 Settable...
Page 402 Nested vectored interrupt controller (NVIC) RM0461 Table 78. Vector table (continued) Type of Acronym Description Address priority 31 38 Settable I2C1_ER I2C1 error interrupt 0x0000 00BC 32 39 Settable I2C2_EV I2C2 event interrupt 0x0000 00C0 33 40 Settable I2C2_ER I2C2 error interrupt 0x0000 00C4 34 41 Settable SPI1...
Page 403 RM0461 Extended interrupts and event controller (EXTI) Extended interrupts and event controller (EXTI) The extended interrupts and event controller (EXTI) manages the individual CPU and system wakeup through configurable and direct event inputs. It provides wakeup requests to the power control and generates an interrupt request to the CPU NVIC and events to the CPU event input.
Page 404: Table 79. Exti Pin Overview
Extended interrupts and event controller (EXTI) RM0461 The masking block provides the event input distribution to the different wakeup, interrupt and event outputs, and the masking of these. Figure 40. EXTI block diagram AHB interface Registers hclk sys_wakeup c_wakeup it_exti_per(y) Masking Wakeup Direct event(x) or...
Page 405: Table 81. Wakeup Interrupts
RM0461 Extended interrupts and event controller (EXTI) 14.3 EXTI connections between peripherals and CPU The peripherals able to generate wakeup or interrupt events when the system is in Stop mode, are connected to the EXTI. Peripheral wakeup signals that generate a pulse or that do not have an interrupt status bits in the peripheral, are connected to an EXTI configurable event input.
Page 406 Extended interrupts and event controller (EXTI) RM0461 Table 81. Wakeup interrupts (continued) EXTI Acronym Description EXTI type Event Wakeup EXTI[15] EXTI line 15 from SYSCFG Configurable PVD line Configurable RTC_ALARM RTC alarms A and B interrupt Direct SSRU RTC SSR underflow interrupt Direct TAMP, TAMP tamper interrupt...
Page 407: Table 82. Exti Event Input Configurations And Register Control
RM0461 Extended interrupts and event controller (EXTI) 14.4 EXTI functional description Depending on the EXTI event input type and wakeup targets, different logic implementations are used. The applicable features are controlled from register bits as detailed below: • Active trigger edge enable –...
Page 408: Figure 41. Configurable Event Trigger Logic Cpu Wakeup
Extended interrupts and event controller (EXTI) RM0461 Figure 41. Configurable event trigger logic CPU wakeup Peripheral interface Falling Rising Software interface Pending trigger trigger interrupt event interrupt request selection selection event mask mask register hclk register register register register register it_exti_per(y) hclk Same circuit for configurable...
Page 409: Table 83. Masking Functionality
RM0461 Extended interrupts and event controller (EXTI) Figure 42. Direct event trigger logic CPU wakeup Peripheral interface interface Same circuit for configurable interrupt event hclk and direct events hclk mask register mask register ck_fclk_c hclk c_evt_rst CPU event(x) Rising edge c_event rising edge c_evt_exti...
Page 410: Table 84. Exti Register Map Sections
Extended interrupts and event controller (EXTI) RM0461 The CPU event must be unmasked in EXTI_EMR to generate an event. When the enabled edges occur on the event input, a CPU event pulse is generated. There is no event pending bit. For the configurable event inputs, an event request can be generated by software, setting to 1 the corresponding bit in the interrupt/event register EXTI_SWIER.
Page 411 RM0461 Extended interrupts and event controller (EXTI) Bit 16 RT16: rising trigger event configuration bit of configurable event input 16 Bit 15 RT15: rising trigger event configuration bit of configurable event input 15 Bit 14 RT14: rising trigger event configuration bit of configurable event input 14 Bit 13 RT13: rising trigger event configuration bit of configurable event input 13 Bit 12 RT12: rising trigger event configuration bit of configurable event input 12 Bit 11 RT11: rising trigger event configuration bit of configurable event input 11...
Page 412 Extended interrupts and event controller (EXTI) RM0461 Bit 16 FT16: falling trigger event configuration bit of configurable event input 16 Bit 15 FT15: falling trigger event configuration bit of configurable event input 15 Bit 14 FT14: falling trigger event configuration bit of configurable event input 14 Bit 13 FT13: falling trigger event configuration bit of configurable event input 13 Bit 12 FT12: falling trigger event configuration bit of configurable event input 12 Bit 11 FT11: falling trigger event configuration bit of configurable event input 11...
Page 413 RM0461 Extended interrupts and event controller (EXTI) Bit 15 SWI15: Software interrupt on line 15 Bit 14 SWI14: Software interrupt on line 14 Bit 13 SWI13: Software interrupt on line 13 Bit 12 SWI12: Software interrupt on line 12 Bit 11 SWI11: Software interrupt on line 11 Bit 10 SWI10: Software interrupt on line 10 Bit 9 SWI9: Software interrupt on line 9 Bit 8 SWI8: Software interrupt on line 8...
Page 414: Exti Rising Trigger Selection Register (Exti_Rtsr2)
Extended interrupts and event controller (EXTI) RM0461 Bit 13 PIF13: pending bit on event input 13 Bit 12 PIF12: pending bit on event input 12 Bit 11 PIF11: pending bit on event input 11 Bit 10 PIF10: pending bit on event input 10 Bit 9 PIF9: pending bit on event input 9 Bit 8 PIF8: pending bit on event input 8 Bit 7 PIF7: pending bit on event input 7...
Page 415: Exti Falling Trigger Selection Register (Exti_Ftsr2)
RM0461 Extended interrupts and event controller (EXTI) 14.6.6 EXTI falling trigger selection register (EXTI_FTSR2) Address offset: 0x024 Reset value: 0x0000 0000 Contains only register bits for configurable events. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 416: Exti Pending Register (Exti_Pr2)
Extended interrupts and event controller (EXTI) RM0461 Bits 31:14 Reserved, must be kept at reset value. Bit 13 SWI45: software interrupt on event 45 A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR. This bit always returns 0 when read. 0: Writing 0 has no effect.
Page 417: Exti Event Mask Register (Exti_Emr1)
RM0461 Extended interrupts and event controller (EXTI) Bits 31:0 IM[31:0]: wakeup with interrupt mask on event input x (x= 31 to 0) For each bit of this field: 0: Wakeup with interrupt request from line x is masked. 1: Wakeup with Interrupt request from line x is unmasked. 14.6.10 EXTI event mask register (EXTI_EMR1) Address offset: 0x084...
Page 418: Table 85. Exti Register Map And Reset Values
Extended interrupts and event controller (EXTI) RM0461 Bit 2 EM2: wakeup with event generation mask on event input 2 Bit 1 EM1: wakeup with event generation mask on event input 1 Bit 0 EM0: wakeup with event generation mask on event input 0 14.6.11 EXTI interrupt mask register (EXTI_IMR2) Address offset: 0x090...
Page 419 RM0461 Extended interrupts and event controller (EXTI) Table 85. EXTI register map and reset values (continued) Offset Register name EXTI_PR1 0x00C Reset value 0x010- Reserved Reserved. 0x01C EXTI_RTSR2 0x020 Reset value EXTI_FTSR2 0x024 Reset value EXTI_SWIER2 0x028 Reset value EXTI_PR2 0x02C Reset value 0x030-...
Page 420 Cyclic redundancy check calculation unit (CRC) RM0461 Cyclic redundancy check calculation unit (CRC) 15.1 Introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16- or 32-bit data word and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
Page 421: Table 86. Crc Internal Input/Output Signals
RM0461 Cyclic redundancy check calculation unit (CRC) 15.3 CRC functional description 15.3.1 CRC block diagram Figure 43. CRC calculation unit block diagram 32-bit AHB bus read access write access 32-bit accesses Data register Data register crc_hclk (output) (input) CRC_INIT CRC_CR CRC computation CRC_POL CRC_IDR...
Page 422 Cyclic redundancy check calculation unit (CRC) RM0461 The data size can be dynamically adjusted to minimize the number of write accesses for a given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write followed by a byte write.
Page 423 RM0461 Cyclic redundancy check calculation unit (CRC) 15.4 CRC registers The CRC_DR register can be accessed by words, right-aligned half-words and right-aligned bytes. For the other registers only 32-bit accesses are allowed. 15.4.1 CRC data register (CRC_DR) Address offset: 0x00 Reset value: 0xFFFF FFFF DR[31:16] DR[15:0]...
Page 424 Cyclic redundancy check calculation unit (CRC) RM0461 15.4.3 CRC control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. REV_ Res. Res. Res. Res. Res.
Page 425 RM0461 Cyclic redundancy check calculation unit (CRC) 15.4.4 CRC initial value (CRC_INIT) Address offset: 0x10 Reset value: 0xFFFF FFFF CRC_INIT[31:16] CRC_INIT[15:0] Bits 31:0 CRC_INIT[31:0]: Programmable initial CRC value This register is used to write the CRC initial value. 15.4.5 CRC polynomial (CRC_POL) Address offset: 0x14 Reset value: 0x04C1 1DB7 POL[31:16]...
Page 426: Table 87. Crc Register Map And Reset Values
Cyclic redundancy check calculation unit (CRC) RM0461 15.4.6 CRC register map Table 87. CRC register map and reset values Register Offset name CRC_DR DR[31:0] 0x00 Reset value CRC_IDR IDR[31:0] 0x04 Reset value CRC_CR 0x08 Reset value CRC_INIT CRC_INIT[31:0] 0x10 Reset value CRC_POL POL[31:0] 0x14...
Page 427 RM0461 Analog-to-digital converter (ADC) Analog-to-digital converter (ADC) 16.1 Introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18 multiplexed channels allowing it to measure signals from 12 external and 4 internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode.
Page 428 Analog-to-digital converter (ADC) RM0461 16.2 ADC main features • High performance – 12-bit, 10-bit, 8-bit or 6-bit configurable resolution – ADC conversion time: 0.4 µs for 12-bit resolution (2.5Msps), faster conversion times can be obtained by lowering resolution. – Self-calibration –...
Page 429: Table 88. Adc Input/Output Pins
RM0461 Analog-to-digital converter (ADC) 16.3 ADC functional description Figure 44 shows the ADC block diagram and Table 88 gives the ADC pin description. Figure 44. ADC block diagram Analog supply VREF+ 1.62 to 3.6 V AREADY SCANDIR EOSMP ADC interrupt IRQ up/down EOSEQ AUTOFF...
Page 430: Table 89. Adc Internal Input/Output Signals
Analog-to-digital converter (ADC) RM0461 Table 89. ADC internal input/output signals Internal signal Signal type Description name Analog Input Connected either to internal channels or to ADC_INi channels external channels TRGx Input ADC conversion triggers Input Internal temperature sensor output voltage Input Internal voltage reference output voltage REFINT...
Page 431 RM0461 Analog-to-digital converter (ADC) regulator of the power control unit operates in normal Run mode (refer to Reset and clock control and power control sections). If the main voltage regulator enters low-power mode (such as Low-power run mode), this buffer is disabled and the ADC cannot be used. ADC Voltage regulator enable sequence To enable the ADC voltage regulator, set ADVREGEN bit to 1 in ADC_CR register.
Page 432: Figure 45. Adc Calibration
Analog-to-digital converter (ADC) RM0461 Software calibration procedure Ensure that ADEN = 0, AUTOFF = 0, ADVREGEN = 1 and DMAEN = 0. Set ADCAL = 1. Wait until ADCAL = 0 (or until EOCAL = 1). This can be handled by interrupt if the interrupt is enabled by setting the EOCALIE bit in the ADC_IER register The calibration factor can be read from bits 6:0 of ADC_DR or ADC_CALFACT registers.
Page 433: Figure 47. Enabling/Disabling The Adc
RM0461 Analog-to-digital converter (ADC) Two control bits are used to enable or disable the ADC: • Set ADEN = 1 to enable the ADC. The ADRDY flag is set as soon as the ADC is ready for operation. • Set ADDIS = 1 to disable the ADC and put the ADC in power down mode. The ADEN and ADDIS bits are then automatically cleared by hardware as soon as the ADC is fully disabled.
Page 434: Figure 48. Adc Clock Scheme
Analog-to-digital converter (ADC) RM0461 16.3.5 ADC clock (CKMODE, PRESC[3:0]) The ADC has a dual clock-domain architecture, so that the ADC can be fed with a clock (ADC asynchronous clock) independent from the APB clock (PCLK). Figure 48. ADC clock scheme ADITF (Reset &...
Page 435: Table 91. Latency Between Trigger And Start Of Conversion
RM0461 Analog-to-digital converter (ADC) Table 91. Latency between trigger and start of conversion Latency between the trigger event ADC clock source CKMODE[1:0] and the start of conversion HSI16, SYSCLK or Latency is not deterministic (jitter) PLLPCLK Latency is deterministic (no jitter) and equal to PCLK divided by 2 3.25 ADC clock cycles Latency is deterministic (no jitter) and equal to...
Page 436: Figure 49. Adc Connectivity
Analog-to-digital converter (ADC) RM0461 16.3.6 ADC connectivity ADC inputs are connected to the external channels as well as internal sources as described Figure Figure 49. ADC connectivity STM32WLxx Channel selection ADC_IN0 ADC_IN1 ADC_IN2 ADC_IN3 ADC_IN4 ADC_IN5 ADC_IN6 REF+ ADC_IN7 ADC_IN8 ADC_IN9 [10] ADC_IN10...
Page 437 RM0461 Analog-to-digital converter (ADC) 16.3.7 Configuring the ADC The software must write the ADCAL and ADEN bits in the ADC_CR register and configure the ADC_CFGR1 and ADC_CFGR2 registers only when the ADC is disabled (ADEN must be cleared). The software must only write to the ADSTART and ADDIS bits in the ADC_CR register only if the ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and ADDIS = 0).
Page 438 Analog-to-digital converter (ADC) RM0461 – Any channel can belong to in these sequences • Sequencer fully configurable The CHSELRMOD bit is set in ADC_CFGR1 register. – Sequencer length is up to 8 channels – The order in which the channels are scanned is independent from the channel number.
Page 439 RM0461 Analog-to-digital converter (ADC) 16.3.10 Single conversion mode (CONT In Single conversion mode, the ADC performs a single sequence of conversions, converting all the channels once. This mode is selected when CONT = 0 in the ADC_CFGR1 register. Conversion is started by either: •...
Page 440 Analog-to-digital converter (ADC) RM0461 16.3.12 Starting conversions (ADSTART) Software starts ADC conversions by setting ADSTART = 1. When ADSTART is set, the conversion: • Starts immediately if EXTEN = 00 (software trigger) • At the next active edge of the selected hardware trigger if EXTEN ≠ 00 The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing.
Page 441: Figure 50. Analog To Digital Conversion Time
RM0461 Analog-to-digital converter (ADC) 16.3.13 Timings The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution: = [1.5 + 12.5 ] x t CONV SMPL...
Page 442: Table 92. Configuring The Trigger Polarity
Analog-to-digital converter (ADC) RM0461 16.3.14 Stopping an ongoing conversion (ADSTP) The software can decide to stop any ongoing conversions by setting ADSTP = 1 in the ADC_CR register. This resets the ADC operation and the ADC is idle, ready for a new operation. When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is discarded (ADC_DR register is not updated with the current conversion).
Page 443 RM0461 Analog-to-digital converter (ADC) Refer to Table 90: External triggers Section 16.3.1: ADC pins and internal signals for the list of all the external triggers that can be used for regular conversion. The software source trigger events can be generated by setting the ADSTART bit in the ADC_CR register.
Page 444: Table 93. Tsar Timings Depending On Resolution
Analog-to-digital converter (ADC) RM0461 Table 93. t timings depending on resolution CONV SMPL (min) RES[1:0] (ns) at (ns) at CONV (ADC clock cycles) (ADC clock (ADC clock bits = 35 MHz = 35 MHz cycles) cycles) (with min. t SMPL 12.5 10.5 16.4.3...
Page 445: Figure 53. Single Conversions Of A Sequence, Software Trigger
RM0461 Analog-to-digital converter (ADC) 16.4.5 Example timing diagrams (single/continuous modes hardware/software triggers) Figure 53. Single conversions of a sequence, software trigger ADSTART SCANDIR ADC state CH17 CH17 CH10 CH10 ADC_DR by S/W by H/W MSv30338V3 1. EXTEN = 00, CONT = 0 2.
Page 446: Figure 55. Single Conversions Of A Sequence, Hardware Trigger
Analog-to-digital converter (ADC) RM0461 Figure 55. Single conversions of a sequence, hardware trigger ADSTART TRGx ADC state ADC_DR by S/W by H/W triggered ignored MSv30340V2 1. EXTSEL = TRGx (over-frequency), EXTEN = 01 (rising edge), CONT = 0 2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0 Figure 56.
Page 447: Figure 57. Data Alignment And Resolution (Oversampling Disabled: Ovse = 0)
RM0461 Analog-to-digital converter (ADC) 16.4.6 Low frequency trigger mode Once the ADC is enabled or the last ADC conversion is complete, the ADC is ready to start a new conversion. The ADC needs to be started at a predefined time (t ) otherwise ADC idle converted data might be corrupted due to the transistor leakage (refer to the device...
Page 448: Figure 58. Example Of Overrun (Ovr)
Analog-to-digital converter (ADC) RM0461 When an overrun condition occurs, the ADC keeps operating and can continue to convert unless the software decides to stop and reset the sequence by setting the ADSTP bit in the ADC_CR register. The OVR flag is cleared by software by writing 1 to it. It is possible to configure if the data is preserved or overwritten when an overrun event occurs by programming the OVRMOD bit in the ADC_CFGR1 register: •...
Page 449 RM0461 Analog-to-digital converter (ADC) 16.5.3 Managing a sequence of data converted without using the DMA If the conversions are slow enough, the conversion sequence can be handled by software. In this case the software must use the EOC flag and its associated interrupt to handle each data result.
Page 450 Analog-to-digital converter (ADC) RM0461 When the DMA transfer is complete (all the transfers configured in the DMA controller have been done): • The content of the ADC data register is frozen. • Any ongoing conversion is aborted and its partial result discarded •...
Page 451: Figure 59. Wait Mode Conversion (Continuous Mode, Software Trigger)
RM0461 Analog-to-digital converter (ADC) Figure 59. Wait mode conversion (continuous mode, software trigger) ADSTART ADSTP ADC_DR Read access STOP ADC state ADC_DR by H/W by S/W MSv30344V2 1. EXTEN = 00, CONT = 1 2. CHSEL = 0x3, SCANDIR = 0, WAIT = 1, AUTOFF = 0 16.6.2 Auto-off mode (AUTOFF) The ADC has an automatic power management feature which is called auto-off mode, and...
Page 452: Figure 60. Behavior With Wait = 0, Autoff = 1
Analog-to-digital converter (ADC) RM0461 Figure 60. Behavior with WAIT = 0, AUTOFF = 1 TRGx ADC_DR Read access Startup Startup ADC state ADC_DR by S/W by H/W triggered MSv30345V2 1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1, AUTOFF = 1 Figure 61.
Page 453: Table 94. Analog Watchdog Comparison
RM0461 Analog-to-digital converter (ADC) 16.7.1 Description of analog watchdog 1 AWD1 analog watchdog is enabled by setting the AWD1EN bit in the ADC_CFGR1 register. It is used to monitor that either one selected channel or all enabled channels (see Table 95: Analog watchdog 1 channel selection) remain within a configured voltage range (window) as shown in...
Page 454 Analog-to-digital converter (ADC) RM0461 Table 95. Analog watchdog 1 channel selection (continued) Channels guarded by the analog watchdog AWD1SGL bit AWD1EN bit All channels Single channel 1. Selected by the AWD1CH[4:0] bits 16.7.2 Description of analog watchdog 2 and 3 The second and third analog watchdogs are more flexible and can guard several selected channels by programming the AWDxCHy in ADC_AWDxCR (x = 2, 3).
Page 455: Figure 63. Adc_Awdx_Out Signal Generation
RM0461 Analog-to-digital converter (ADC) The AWD comparison is performed at the end of each ADC conversion. The ADC_AWDx_OUT rising edge and falling edge occurs two ADC_CLK clock cycles after the comparison. As ADC_AWDx_OUT is generated by the ADC_CLK domain and AWD flag is generated by the APB clock domain, the rising edges of these signals are not synchronized.
Page 456: Figure 65. Adc_Awdx_Out Signal Generation (On A Single Channel)
Analog-to-digital converter (ADC) RM0461 Figure 65. ADC_AWDx_OUT signal generation (on a single channel) ADC STATE Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2 outside inside outside outside EOC FLAG EOS FLAG Cleared Cleared by SW by SW AWDx FLAG ADCy_AWDx_OUT - Converted channels: 1 and 2 - Only channel 1 is guarded MSv45364V1...
Page 457: Figure 67. 20-Bit To 16-Bit Result Truncation
RM0461 Analog-to-digital converter (ADC) 16.8 Oversampler The oversampling unit performs data preprocessing to offload the CPU. It can handle multiple conversions and average them into a single data with increased data width, up to 16-bit. It provides a result with the following form, where N and M can be adjusted: –...
Page 458: Table 96. Maximum Output Results Vs N And M. Grayed Values Indicates Truncation
Analog-to-digital converter (ADC) RM0461 Figure 68. Numerical example with 5-bits shift and rounding Raw 20-bit data: Final result after 5-bits shift and rounding to nearest MS31929V1 Table 96 below gives the data format for the various N and M combination, for a raw conversion data equal to 0xFFF.
Page 459 RM0461 Analog-to-digital converter (ADC) 16.8.1 ADC operating modes supported when oversampling In oversampling mode, most of the ADC operating modes are available: • Single or continuous mode conversions, forward or backward scanned sequences and up to 8 channels programmed sequence •...
Page 460: Figure 69. Triggered Oversampling Mode (Tovs Bit = 1)
Analog-to-digital converter (ADC) RM0461 Figure 69. Triggered oversampling mode (TOVS bit = 1) Trigger Trigger CONT = 0 Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) (DISCEN = 1)* TOVS = 0 EOC flag set Trigger Trigger Trigger Trigger Trigger Trigger Trigger CONT = 0...
Page 461: Figure 70. Temperature Sensor And Vrefint Channel Block Diagram
RM0461 Analog-to-digital converter (ADC) Main features • Linearity: ±2 °C max., precision depending on calibration Figure 70. Temperature sensor and V channel block diagram REFINT TSEN control bit Temperature sensor ADC V [12] converted data VREFEN control bit REFINT ADC V [13] Internal power block...
Page 462 Analog-to-digital converter (ADC) RM0461 Calculating the actual V voltage using the internal reference voltage REF+ voltage may be subject to variation or not precisely known. The embedded internal REF+ reference voltage (V ) and its calibration data acquired by the ADC during the REFINT manufacturing process at V can be used to evaluate the actual V...
Page 463: Table 97. Adc Interrupts
RM0461 Analog-to-digital converter (ADC) the correct operation of the ADC, the VBAT pin is internally connected to a bridge divider. This bridge is automatically enabled when VBATEN is set, to connect V to the ADC [14] input channel. As a consequence, the converted digital value is V /3.
Page 464 Analog-to-digital converter (ADC) RM0461 Table 97. ADC interrupts (continued) Interrupt event Event flag Enable control bit Analog watchdog 2 status bit is set AWD2 AWD2IE Analog watchdog 3 status bit is set AWD3 AWD3IE Channel Configuration Ready CCRDY CCRDYIE End of sampling phase EOSMP EOSMPIE Overrun...
Page 465 RM0461 Analog-to-digital converter (ADC) 16.12 ADC registers Refer to Section 1.2 for a list of abbreviations used in register descriptions. 16.12.1 ADC interrupt and status register (ADC_ISR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res.
Page 466 Analog-to-digital converter (ADC) RM0461 Bit 7 AWD1: Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1. 0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) 1: Analog watchdog event occurred...
Page 467 RM0461 Analog-to-digital converter (ADC) 16.12.2 ADC interrupt enable register (ADC_IER) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CCRD EOCAL AWD3I AWD2I AWD1I EOSMP ADRDY Res.
Page 468 Analog-to-digital converter (ADC) RM0461 Bit 4 OVRIE: Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. 0: Overrun interrupt disabled 1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).
Page 469 RM0461 Analog-to-digital converter (ADC) 16.12.3 ADC control register (ADC_CR) Address offset: 0x08 Reset value: 0x0000 0000 ADVR ADCAL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EGEN ADSTA Res. Res. Res. Res. Res. Res. Res.
Page 470 Analog-to-digital converter (ADC) RM0461 Bit 2 ADSTART: ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration).
Page 471 RM0461 Analog-to-digital converter (ADC) 16.12.4 ADC configuration register 1 (ADC_CFGR1) Address offset: 0x0C Reset value: 0x0000 0000 The software is allowed to program ADC_CFGR1 only when ADEN is cleared in ADC_CR. AWD1E AWD1SG CHSEL Res. AWD1CH[4:0] Res. Res. Res. Res. Res.
Page 472 Analog-to-digital converter (ADC) RM0461 Bit 16 DISCEN: Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. 0: Discontinuous mode disabled 1: Discontinuous mode enabled Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.
Page 473 RM0461 Analog-to-digital converter (ADC) Bits 8:6 EXTSEL[2:0]: External trigger selection These bits select the external event used to trigger the start of conversion (refer to Table 90: External triggers for details): 000: TRG0 001: TRG1 010: TRG2 011: TRG3 100: TRG4 101: TRG5 110: TRG6 111: TRG7...
Page 474 Analog-to-digital converter (ADC) RM0461 16.12.5 ADC configuration register 2 (ADC_CFGR2) Address offset: 0x10 Reset value: 0x0000 0000 The software is allowed to program ADC_CFGR2 only when ADEN is cleared in ADC_CR. CKMODE[1:0] LFTRIG Res. Res. Res. Res. Res. Res. Res. Res.
Page 475 RM0461 Analog-to-digital converter (ADC) Bits 8:5 OVSS[3:0]: Oversampling shift This bit is set and cleared by software. 0000: No shift 0001: Shift 1-bit 0010: Shift 2-bits 0011: Shift 3-bits 0100: Shift 4-bits 0101: Shift 5-bits 0110: Shift 6-bits 0111: Shift 7-bits 1000: Shift 8-bits Others: Reserved Note: The software is allowed to write this bit only when ADEN bit is cleared.
Page 476 Analog-to-digital converter (ADC) RM0461 Bits 31:26 Reserved, must be kept at reset value. Bits 25:8 SMPSELx: Channel-x sampling time selection (x = 17 to 0) These bits are written by software to define which sampling time is used. 0: Sampling time of CHANNELx use the setting of SMP1[2:0] register. 1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Page 477 RM0461 Analog-to-digital converter (ADC) Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to Section 16.7: Analog window watchdogs on page 452.
Page 478 Analog-to-digital converter (ADC) RM0461 16.12.9 ADC channel selection register (ADC_CHSELR) Address offset: 0x28 Reset value: 0x0000 0000 The same register can be used in two different modes: – Each ADC_CHSELR bit enables an input (CHSELRMOD = 0 in ADC_CFGR1). Refer to the current section.
Page 479 RM0461 Analog-to-digital converter (ADC) 16.12.10 ADC channel selection register [alternate] (ADC_CHSELR) Address offset: 0x28 Reset value: 0x0000 0000 The same register can be used in two different modes: – Each ADC_CHSELR bit enables an input (CHSELRMOD = 0 in ADC_CFGR1). Refer to the current previous section.
Page 480 Analog-to-digital converter (ADC) RM0461 Bits 19:16 SQ5[3:0]: 5th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.
Page 481 RM0461 Analog-to-digital converter (ADC) 16.12.11 ADC watchdog threshold register (ADC_AWD3TR) Address offset: 0x2C Reset value: 0x0FFF 0000 Res. Res. Res. Res. HT3[11:0] Res. Res. Res. Res. LT3[11:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 HT3[11:0]: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog.
Page 482 Analog-to-digital converter (ADC) RM0461 16.12.13 ADC Analog Watchdog 2 Configuration register (ADC_AWD2CR) Address offset: 0xA0 Reset value: 0x0000 0000 AWD2 AWD2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CH17 CH16 AWD2 AWD2 AWD2 AWD2 AWD2 AWD2...
Page 483 RM0461 Analog-to-digital converter (ADC) 16.12.15 ADC Calibration factor (ADC_CALFACT) Address offset: 0xB4 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 484: Table 98. Adc Register Map And Reset Values
Analog-to-digital converter (ADC) RM0461 Bits 31:25 Reserved, must be kept at reset value. Bit 24 VBATEN: V enable This bit is set and cleared by software to enable/disable the V channel. 0: V channel disabled 1: V channel enabled Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing) Bit 23 TSEN: Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor.
Page 485 RM0461 Analog-to-digital converter (ADC) Table 98. ADC register map and reset values (continued) Offset Register ADC_IER 0x04 Reset value ADC_CR 0x08 Reset value EXTSEL ADC_CFGR1 AWDCH[4:0] [2:0] [1:0] 0x0C Reset value ADC_CFGR2 0x10 Reset value SMP2 SMP1 ADC_SMPR 0x14 [2:0] [2:0] Reset value 0x18...
Page 486 Analog-to-digital converter (ADC) RM0461 Table 98. ADC register map and reset values (continued) Offset Register 0xA4 ADC_AWD3CR Reset value Reserved Reserved ADC_CALFACT CALFACT[6:0] 0xB4 Reset value Reserved Reserved ADC_CCR 0x308 Reset value Refer to Section 2.4 on page 62 for the register boundary addresses. 486/1306 RM0461 Rev 5...
Page 487 RM0461 Digital-to-analog converter (DAC) Digital-to-analog converter (DAC) 17.1 Introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned.
Page 488: Table 99. Dac Features
Digital-to-analog converter (DAC) RM0461 17.3 DAC implementation Table 99. DAC features DAC features Dual channel Output buffer I/O connection DAC_OUT1 to PA10 Maximum sampling time 1 Msps Autonomous mode VREF+ pin 17.4 DAC functional description 17.4.1 DAC block diagram Figure 72. DAC block diagram Offset calibration dac_ch1_trg1...
Page 489: Table 100. Dac Input/Output Pins
RM0461 Digital-to-analog converter (DAC) 17.4.2 DAC pins and internal signals The DAC includes: • One output channel • The DACx_OUT1 can be disconnected from the output pin and used as an ordinary GPIO • The dac_out1 can use an internal pin connection to on-chip peripherals such as comparator, operational amplifier and ADC (if available).
Page 490: Figure 73. Data Registers In Single Dac Channel Mode
Digital-to-analog converter (DAC) RM0461 Table 102. DAC interconnection (continued) Signal name Source Source type Internal signal from on-chip dac_ch1_trg2 tim2_trgo timers TIM2_TGO_CKTIM Internal signal from on-chip dac_ch1_trg11 lptim1_out timers LPTIM1_OUT Internal signal from on-chip dac_ch1_trg12 lptim2_out timers LPTIM2_OUT Internal signal from on-chip dac_ch1_trg13 lptim3_out timers LPTIM3_OUT...
Page 491: Figure 74. Timing Diagram For Conversion With Trigger Disabled Ten = 0
RM0461 Digital-to-analog converter (DAC) 17.4.5 DAC conversion The DAC_DOR1 cannot be written directly and any data transfer to the DAC channel1 must be performed by loading the DAC_DHR1 register (write operation to DAC_DHR8R1, DAC_DHR12L1, DAC_DHR12R1, DAC_DHR8RD, DAC_DHR12RD or DAC_DHR12LD). Data stored in the DAC_DHR1 register are automatically transferred to the DAC_DOR1 register after one dac_pclk clock cycle, if no hardware trigger is selected (TEN1 bit in DAC_CR register is reset).
Page 492 Digital-to-analog converter (DAC) RM0461 If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DOR1 register has been loaded with the DAC_DHR1 register contents. Note: TSEL1[3:0] bit cannot be changed when the EN1 bit is set. When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle.
Page 493: Figure 75. Dac Lfsr Register Calculation Algorithm
RM0461 Digital-to-analog converter (DAC) Figure 75. DAC LFSR register calculation algorithm ai14713c The LFSR value, that may be masked partially or totally by means of the MAMP1[3:0] bits in the DAC_CR register, is added up to the DAC_DHR1 contents without overflow and this value is then transferred into the DAC_DOR1 register.
Page 494: Figure 77. Dac Triangle Wave Generation
Digital-to-analog converter (DAC) RM0461 17.4.10 Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVE1[1:0] to 10”. The amplitude is configured through the MAMP1[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three dac_pclk clock cycles after each trigger event.
Page 495 RM0461 Digital-to-analog converter (DAC) 17.4.11 DAC channel modes The DAC channel can be configured in Normal mode or Sample and hold mode. The output buffer can be enabled to obtain a high drive capability. Before enabling output buffer, the voltage offset needs to be calibrated. This calibration is performed at the factory (loaded after reset) and can be adjusted by software during application operation.
Page 496: Table 103. Sample And Refresh Timings
Digital-to-analog converter (DAC) RM0461 The timings for the three phases above are in units of LSI clock periods. As an example, to configure a sample time of 350 µs, a hold time of 2 ms and a refresh time of 100 µs assuming LSI ~32 KHz is selected: 12 cycles are required for sample phase: TSAMPLE1[9:0] = 11, 62 cycles are required for hold phase: THOLD1[9:0] = 62,...
Page 497: Table 104. Channel Output Modes Summary
RM0461 Digital-to-analog converter (DAC) Figure 79. DAC Sample and hold mode phase diagram Sampling phase Hold phase Sampling phase Refresh dac_hold phase MSv45340V3 Like in Normal mode, the Sample and hold mode has different configurations. To enable the output buffer, MODE1[2:0] bits in DAC_MCR register must be set to: •...
Page 498 Digital-to-analog converter (DAC) RM0461 Table 104. Channel output modes summary (continued) MODE [2:0] Mode Buffer Output connections Connected to external pin Enabled Connected to external pin and to on chip peripherals (such as comparators) Sample and hold mode Connected to external pin and to on chip peripherals (such as comparators) Disabled Connected to on chip peripherals (such as comparators)
Page 499 RM0461 Digital-to-analog converter (DAC) If the DAC channel is active, write 0 to EN1 bit in DAC_CR to disable the channel. Select a mode where the buffer is enabled, by writing to DAC_MCR register, MODE1[2:0] = 000b or 001b or 100b or 101b. Start the DAC channel calibration, by setting the CEN1 bit in DAC_CR register to 1.
Page 500: Table 105. Effect Of Low-Power Modes On Dac
Digital-to-analog converter (DAC) RM0461 Independent trigger with single LFSR generation To configure the DAC in this conversion mode, the following sequence is required: Set the DAC channel trigger enable bit, TEN1. Configure the trigger sources by setting different values in the TSEL1[3:0] bits. Configure the DAC channel WAVE1[1:0] bits as 01 and the same LFSR mask value in the MAMP1[3:0] bits.
Page 501: Table 106. Dac Interrupts
RM0461 Digital-to-analog converter (DAC) Table 105. Effect of low-power modes on DAC (continued) Mode Description The DAC remains active with a static value if the Sample and hold mode is Stop 0 / Stop 1 selected using LSI clock. The DAC registers content is lost and must be reinitialized after exiting Stop 2 Stop 2.
Page 502 Digital-to-analog converter (DAC) RM0461 17.7 DAC registers Refer to Section 1 on page 55 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 17.7.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 Res.
Page 503 RM0461 Digital-to-analog converter (DAC) Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15...
Page 504 Digital-to-analog converter (DAC) RM0461 17.7.2 DAC software trigger register (DAC_SWTRGR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 505 RM0461 Digital-to-analog converter (DAC) 17.7.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC1DHR[11:0] Res. Res. Res.
Page 506 Digital-to-analog converter (DAC) RM0461 Res. Res. Res. Res. DACC1DHR[11:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 17.7.7 Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD)
Page 507 RM0461 Digital-to-analog converter (DAC) 17.7.9 DAC channel1 data output register (DAC_DOR1) Address offset: 0x2C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC1DOR[11:0] Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1.
Page 508 Digital-to-analog converter (DAC) RM0461 Bit 13 DMAUDR1: DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 0: No DMA underrun error condition occurred for DAC channel1 1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) Bit 12 Reserved, must be kept at reset value.
Page 509 RM0461 Digital-to-analog converter (DAC) Bit 8 Reserved, must be kept at reset value. Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 MODE1[2:0]: DAC channel1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1 = 0 and bit CEN1 = 0 in the DAC_CR register).
Page 510 Digital-to-analog converter (DAC) RM0461 17.7.14 DAC sample and hold time register (DAC_SHHR) Address offset: 0x48 Reset value: 0x0001 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 511: Table 107. Dac Register Map And Reset Values
RM0461 Digital-to-analog converter (DAC) 17.7.16 DAC register map Table 107 summarizes the DAC registers. Table 107. DAC register map and reset values Register Offset name DAC_CR 0x00 Reset value DAC_ SWTRGR 0x04 Reset value DAC_ DACC1DHR[11:0] DHR12R1 0x08 Reset value DAC_ DACC1DHR[11:0] DHR12L1...
Page 512 Digital-to-analog converter (DAC) RM0461 Table 107. DAC register map and reset values (continued) Register Offset name DAC_ TREFRESH1[7:0] SHRR 0x4C Reset value Refer to Section 2.4 on page 62 for the register boundary addresses. 512/1306 RM0461 Rev 5...
Page 513: Table 108. Vref Buffer Modes
RM0461 Voltage reference buffer (VREFBUF) Voltage reference buffer (VREFBUF) 18.1 Introduction The devices embed a voltage reference buffer which can be used as voltage reference for ADC, DAC and also as voltage reference for external components through the VREF+ pin.When the VREF+ pin is double-bonded with VDDA pin in a package, the voltage reference buffer is not available and must be kept disabled (refer to datasheet for packages pinout description).
Page 514 Voltage reference buffer (VREFBUF) RM0461 18.3 VREFBUF registers 18.3.1 VREFBUF control and status register (VREFBUF_CSR) Address offset: 0x00 Reset value: 0x0000 0002 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 515: Table 109. Vrefbuf Register Map And Reset Values
RM0461 Voltage reference buffer (VREFBUF) Bits 31:6 Reserved, must be kept at reset value. Bits 5:0 TRIM[5:0]: Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows the tuning of the internal reference buffer voltage.
Page 516 Comparator (COMP) RM0461 Comparator (COMP) 19.1 COMP introduction The device embeds two ultra-low-power comparators (COMP1 and COMP2). These comparators can be used for a variety of functions including the following: • wake up from low-power mode triggered by an analog signal •...
Page 517: Table 110. Comp1 Input Plus Assignment
RM0461 Comparator (COMP) 19.3 COMP functional description 19.3.1 COMP block diagram The block diagram of the comparators is shown in the figure below. Figure 80. Comparator block diagram COMPx_INPSEL GPIO alternate function COMPx_POL COMPx_INP COMPx_OUT COMPx_INP I/Os COMPx COMPx_INM COMPx_VALUE COMPx_ COMPx_INMESEL Wakeup EXTI...
Page 518: Table 111. Comp1 Input Minus Assignment
Comparator (COMP) RM0461 Table 111. COMP1 input minus assignment COMP1_INM COMP1_INMSEL[2:0] COMP1_INMESEL[1:0] 1/4 V Not affected REFINT 1/2 V Not affected REFINT 3/4 V Not affected REFINT Not affected REFINT DAC channel1 Not affected Reserved Not affected Not affected PA10 PA11 PA15 Reserved...
Page 519 RM0461 Comparator (COMP) 19.3.3 COMP reset and clocks The COMP clock provided by the clock controller is synchronous with the APB2 clock. There is no clock enable control bit provided in the RCC controller. Reset and clock enable bits are common for COMP and SYSCFG. Note: Important: The polarity selection logic and the output redirection to the port works independently from the APB2 clock.
Page 520: Figure 81. Window Mode
Comparator (COMP) RM0461 Figure 81. Window mode COMPx_INPSEL COMPx_INP COMPx_INP I/Os COMPx COMPx_INM COMPx_INMSEL COMPx_INMESEL COMPx_INM I/Os COMPx_INM I/Os Internal sources WINMODE COMPx_INPSEL COMPy_INP COMPy_INP I/Os COMPy COMPy_INM COMPy_INMSEL COMPy_INMESEL COMPy_INM I/Os COMPy_INM I/Os Internal sources MSv37667V1 19.3.6 Hysteresis The comparator includes a programmable hysteresis to avoid spurious output transitions in case of noisy signals.
Page 521: Figure 83. Comparator Output Blanking
RM0461 Comparator (COMP) 19.3.7 Comparator output blanking function The purpose of the blanking function is to prevent the current regulation to trip upon short current spikes at the beginning of the PWM period (typically the recovery current in power switches anti parallel diodes). It uses a blanking window defined with a timer output compare signal.
Page 522: Table 114. Comparator Behavior In The Low-Power Modes
Comparator (COMP) RM0461 19.4 COMP low-power modes Table 114. Comparator behavior in the low-power modes Mode Description No effect on the comparators Sleep Comparator interrupts cause the device to exit the Sleep mode. LPRun No effect No effect on the comparators LPSleep Comparator interrupts cause the device to exit the LPSleep mode.
Page 523 RM0461 Comparator (COMP) 19.6 COMP registers 19.6.1 COMP1 control and status register (COMP1_CSR) Address offset: 0x00 Reset value: 0x0000 0000 SCAL LOCK VALUE Res. Res. Res. INMESEL[1:0] Res. BRGEN Res. BLANKING[2:0] HYST[1:0] POLA Res. Res. Res. Res. Res. Res. INPSEL[1:0] INMSEL[2:0] PWRMODE[1:0] Res.
Page 524 Comparator (COMP) RM0461 Bits 20:18 BLANKING[2:0]: COMP1 blanking source selection These bits select which timer output controls the COMP1 output blanking. 000: No blanking 001: TIM1 OC5 selected as blanking source 010: TIM2 OC3 selected as blanking source Others: reserved Bits 17:16 HYST[1:0]: COMP1 hysteresis selection These bits are set and cleared by software.
Page 525 RM0461 Comparator (COMP) 19.6.2 COMP2 control and status register (COMP2_CSR) Address offset: 0x04 Reset value: 0x0000 0000 SCAL LOCK VALUE Res. Res. Res. INMESEL[1:0] Res. BRGEN Res. BLANKING[2:0] HYST[1:0] POLA Res. Res. Res. Res. Res. INPSEL[1:0] INMSEL[2:0] PWRMODE[1:0] Res. RITY MODE Bit 31 LOCK: locks the whole content of the register, COMP2_CSR[31:0] This bit is set by software and cleared by a hardware system reset.
Page 526 Comparator (COMP) RM0461 Bits 20:18 BLANKING[2:0]: COMP2 blanking source selection These bits select which timer output controls the COMP2 output blanking. 000: No blanking 001: TIM1 OC5 selected as blanking source 010: TIM2 OC3 selected as blanking source Others: reserved Bits 17:16 HYST[1:0]: COMP2 hysteresis selection These bits are set and cleared by software.
Page 527: Table 116. Comp Register Map And Reset Values
RM0461 Comparator (COMP) Bit 0 EN: COMP2 enable This bit is set and cleared by software. It switches COMP2 on. 0: COMP2 switched off 1: COMP2 switched on 19.6.3 COMP register map Table 116. COMP register map and reset values Offset Register name COMP1_CSR 0x00...
Page 528 True random number generator (RNG) RM0461 True random number generator (RNG) 20.1 Introduction The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. It is composed of a live entropy source (analog) and an internal conditioning component.
Page 529: Table 117. Rng Internal Input/Output Signals
RM0461 True random number generator (RNG) 20.3 RNG functional description 20.3.1 RNG block diagram Figure 84 shows the RNG block diagram. Figure 84. RNG block diagram True RNG rng_it Conditioning logic Banked Registers CONDRST RNG_CR RNG_DR RNG_SR interface Fault detection Clock checker rng_hclk 1-bit...
Page 530: Figure 85. Nist Sp800-90B Entropy Source Model
True random number generator (RNG) RM0461 20.3.3 Random number generation The true random number generator (RNG) delivers truly random data through its AHB interface at deterministic intervals. Within its boundary RNG integrates all the required NIST components depicted on Figure 85.
Page 531 RM0461 True random number generator (RNG) Post processing In NIST configuration no post-processing is applied to sampled noise source. In non-NIST configuration B (as defined in Section 20.6.2) a normalization debiasing is applied, that is half of the bits are taken from the sampled noise source, half of the bits are taken from inverted sampled noise source.
Page 532 True random number generator (RNG) RM0461 Health checks This component ensures that the entire entropy source (with its noise source) starts then operates as expected, obtaining assurance that failures are caught quickly and with a high probability and reliability. The RNG implements the following health check features in accordance with NIST SP800-90B.
Page 533: Figure 86. Rng Initialization Overview
RM0461 True random number generator (RNG) 20.3.4 RNG initialization The RNG simplified state machine is pictured on Figure After enabling the RNG (RNGEN = 1 in RNG_CR) the following chain of events occurs: The analog noise source is enabled, and by default the RNG waits 16 cycles of RNG clock cycles (before divider) before starting to sample analog output and filling 128-bit conditioning shift register.
Page 534 True random number generator (RNG) RM0461 Figure 86 also highlights a possible software reset sequence, implemented by: Writing bits RNGEN = 0 and CONDRST = 1 in the RNG_CR register with the same RNG configuration and a new CLKDIV if needed. Then writing RNGEN = 1 and CONDRST = 0 in the RNG_CR register.
Page 535 RM0461 True random number generator (RNG) additional words can be read by the application (in this case the DRDY bit is still high). If one or both of above conditions are false, the RNG_DR register must not be read. If an error occurred error recovery sequence described in Section 20.3.7 must be used.
Page 536 True random number generator (RNG) RM0461 CEIS is set only when CECS is set to 1 by RNG. Noise source error detection When a noise source (or seed) error occurs, the RNG stops generating random numbers and sets to 1 both SEIS and SECS bits to indicate that a seed error occurred. If a value is available in the RNG_DR register, it must not be used as it may not have enough entropy.
Page 537: Table 118. Rng Interrupt Requests
20.6.1 Introduction In order to assess the amount of entropy available from the RNG, STMicroelectronics has tested the peripheral using German BSI AIS-31 statistical tests (T0 to T8), and NIST SP800-90B test suite. The results can be provided on demand or the customer can reproduce the tests.
Page 538: Table 119. Rng Configurations
“STM32 microcontrollers random number generation validation using NIST statistical test suite” application note (AN4230) available from www.st.com. Contact STMicroelectronics if above samples need to be retrieved for the product. 20.7 RNG registers The RNG is associated with a control register, a data register and a status register.
Page 539 RM0461 True random number generator (RNG) Bit 31 CONFIGLOCK: RNG Config lock 0: Writes to the RNG_HTCR and RNG_CR configuration bits [29:4] are allowed. 1: Writes to the RNG_HTCR and RNG_CR configuration bits [29:4] are ignored until the next RNG reset. This bitfield is set once: if this bit is set it can only be reset to 0 if RNG is reset.
Page 540 True random number generator (RNG) RM0461 Bit 5 CED: Clock error detection 0: Clock error detection is enable 1: Clock error detection is disable The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, that is to enable or disable CED the RNG must be disabled. Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0.
Page 541 RM0461 True random number generator (RNG) 20.7.2 RNG status register (RNG_SR) Address offset: 0x004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 542 True random number generator (RNG) RM0461 20.7.3 RNG data register (RNG_DR) Address offset: 0x008 Reset value: 0x0000 0000 The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY = 1 and value is not 0x0, even if RNGEN = 0.
Page 543: Table 120. Rng Register Map And Reset Map
RM0461 True random number generator (RNG) 20.7.5 RNG register map Table 120. RNG register map and reset map Offset Register name RNG_C RNG_CO .CLKDIV RNG_CONFIG1 RNG_CR ONFIG NFIG3 [3:0] [5:0] 0x000 2[2:0] [3:0] Reset value 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RNG_SR 0x004 Reset value...
Page 544 AES hardware accelerator (AES) RM0461 AES hardware accelerator (AES) 21.1 Introduction The AES hardware accelerator (AES) encrypts or decrypts data, using an algorithm and implementation fully compliant with the advanced encryption standard (AES) defined in Federal information processing standards (FIPS) publication 197. The peripheral supports CTR, GCM, GMAC, CCM, ECB, and CBC chaining modes for key sizes of 128 or 256 bits.
Page 545: Table 121. Aes Internal Input/Output Signals
RM0461 AES hardware accelerator (AES) 21.3 AES implementation The devices have one AES peripheral. 21.4 AES functional description 21.4.1 AES block diagram Figure 87 shows the block diagram of AES. Figure 87. AES block diagram 32-bit Banked registers access AES_KEYRx 32-bit AHB bus AES_IVRx...
Page 546 AES hardware accelerator (AES) RM0461 21.4.3 AES cryptographic core Overview The AES cryptographic core consists of the following components: • AES core algorithm (AEA) • multiplier over a binary Galois field (GF2mul) • key input • initialization vector (IV) input •...
Page 547: Figure 88. Ecb Encryption And Decryption Principle
RM0461 AES hardware accelerator (AES) Note: The chaining mode may be changed only when AES is disabled (bit EN of the AES_CR register cleared). Principle of each AES chaining mode is provided in the following subsections. Detailed information is in dedicated sections, starting from Section 21.4.8: AES basic chaining modes (ECB, CBC).
Page 548: Figure 89. Cbc Encryption And Decryption Principle
AES hardware accelerator (AES) RM0461 Cipher block chaining (CBC) mode Figure 89. CBC encryption and decryption principle Encryption Plaintext block 1 Plaintext block 2 Plaintext block 3 initialization vector Encrypt Encrypt Encrypt Ciphertext block 1 Ciphertext block 2 Ciphertext block 3 Decryption Plaintext block 1 Plaintext block 2...
Page 549: Figure 90. Ctr Encryption And Decryption Principle
RM0461 AES hardware accelerator (AES) Counter (CTR) mode Figure 90. CTR encryption and decryption principle Encryption Counter Counter Counter value value + 1 value + 2 Encrypt Encrypt Encrypt Plaintext block 1 Plaintext block 2 Plaintext block 3 Ciphertext block 1 Ciphertext block 2 Ciphertext block 3 Decryption...
Page 550: Figure 91. Gcm Encryption And Authentication Principle
AES hardware accelerator (AES) RM0461 Galois/counter mode (GCM) Figure 91. GCM encryption and authentication principle Initialization Counter Counter Counter vector value value + 1 value + 2 Init Encrypt Encrypt Encrypt (Encrypt) Plaintext block 1 Plaintext block 2 Plaintext block 3 Ciphertext block 1 Ciphertext block 2 Ciphertext block 3...
Page 551: Figure 93. Ccm Encryption And Authentication Principle
RM0461 AES hardware accelerator (AES) GMAC is similar to GCM, except that it is applied on a message composed only by plaintext authenticated data (that is, only header, no payload). Counter with CBC-MAC (CCM) principle Figure 93. CCM encryption and authentication principle Count 1 Count 2 Count 3...
Page 552 AES hardware accelerator (AES) RM0461 Initialization of AES To initialize AES, first disable it by clearing the EN bit of the AES_CR register. Then perform the following steps in any order: • Configure the AES mode, by programming the MODE[1:0] bitfield of the AES_CR register.
Page 553 RM0461 AES hardware accelerator (AES) Data append using interrupt The method uses interrupt from the AES peripheral to control the data append, through the following sequence: Enable interrupts from AES by setting the CCFIE bit of the AES_CR register. Enable the AES peripheral by setting the EN bit of the AES_CR register. Write first four input data words into the AES_DINR register.
Page 554 AES hardware accelerator (AES) RM0461 21.4.5 AES decryption round key preparation Internal key schedule is used to generate AES round keys. In AES encryption, the round 0 key is the one stored in the key registers. AES decryption must start using the last round key.
Page 555: Figure 94. Example Of Suspend Mode Management
RM0461 AES hardware accelerator (AES) 21.4.7 AES task suspend and resume A message can be suspended if another message with a higher priority must be processed. When this highest priority message is sent, the suspended message can resume in both encryption or decryption mode.
Page 556: Figure 95. Ecb Encryption
AES hardware accelerator (AES) RM0461 Figure 95 illustrates the electronic codebook (ECB) encryption. Figure 95. ECB encryption Block 1 Block 2 AES_DINR (plaintext P1) AES_DINR (plaintext P2) Swap Swap DATATYPE[1:0] DATATYPE[1:0] management management AES_KEYRx (KEY) AES_KEYRx (KEY) Encrypt Encrypt Legend AES core Swap Swap...
Page 557: Figure 97. Cbc Encryption
RM0461 AES hardware accelerator (AES) Figure 97 illustrates the cipher block chaining (CBC) encryption. Figure 97. CBC encryption Block 1 Block 2 AES_DINR (plaintext P1) AES_DINR (plaintext P2) Swap Swap DATATYPE[1:0] DATATYPE[1:0] management management AES_IVRx (init. vector) AES_KEYRx (KEY) AES_KEYRx (KEY) Block cipher Block cipher encryption...
Page 558: Figure 99. Ecb/Cbc Encryption (Mode 1)
AES hardware accelerator (AES) RM0461 The second ciphertext block is processed in the same way as the first block, except that the I1 data from the first block is used in place of the initialization vector. The decryption continues in this way until the last complete ciphertext block is decrypted. If the message size is not a multiple of 128 bits, the final partial data block is decrypted in the way explained in Section 21.4.6: AES ciphertext stealing and data...
Page 559: Figure 100. Ecb/Cbc Decryption (Mode 3)
RM0461 AES hardware accelerator (AES) register to 000 or 001, respectively. Data type can also be defined, using DATATYPE[1:0] bitfield. KEYSIZE bitfield must be kept as-is. Write the AES_IVRx registers with the initialization vector (required in CBC mode only). Enable AES by setting the EN bit of the AES_CR register. Write the AES_DINR register four times to input the cipher text (MSB first), as shown in Figure 100.
Page 560: Figure 101. Message Construction In Ctr Mode
AES hardware accelerator (AES) RM0461 To resume the processing of a message, proceed as follows: If DMA is used, configure the DMA controller so as to complete the rest of the FIFO IN and FIFO OUT transfers. Disable the AES peripheral by clearing the EN bit of the AES_CR register. Restore AES_CR register (with correct KEYSIZE) then restore AES_KEYRx registers.
Page 561: Table 122. Ctr Mode Initialization Vector Definition
RM0461 AES hardware accelerator (AES) CTR encryption and decryption Figure 102 Figure 103 describe the CTR encryption and decryption process, respectively, as implemented in the AES peripheral. The CTR mode is selected by writing 010 to the CHMOD[2:0] bitfield of AES_CR register. Figure 102.
Page 562 AES hardware accelerator (AES) RM0461 Unlike in CBC mode that uses the AES_IVRx registers only once when processing the first data block, in CTR mode AES_IVRx registers are used for processing each data block, and the AES peripheral increments the counter bits of the initialization vector (leaving the nonce bits unchanged).
Page 563: Table 123. Gcm Last Block Definition
RM0461 AES hardware accelerator (AES) Figure 104. Message construction in GCM [Len(A)] [Len(C)] Len(A) Len(P) = Len(C) 16-byte boundaries Additional authenticated data Last Plaintext (P) (AAD) block 4-byte boundaries Authenticated & encrypted ciphertext (C) Initialization vector (IV) Counter Authentication tag (T) Zero padding / zeroed bits MSv42157V1 The message has the following structure:...
Page 564: Table 124. Initialization Of Aes_Ivrx Registers In Gcm Mode
AES hardware accelerator (AES) RM0461 GCM processing Figure 105 describes the GCM implementation in the AES peripheral. The GCM is selected by writing 011 to the CHMOD[2:0] bitfield of the AES_CR register. Figure 105. GCM authenticated encryption (3) Payload Block 1 Block n AES_IVRx ICB + (32-bit counter = 0x02)
Page 565 RM0461 AES hardware accelerator (AES) The authentication mechanism in GCM mode is based on a hash function called GF2mul that performs multiplication by a fixed parameter, called hash subkey (H), within a binary Galois field. A GCM message is processed through the following phases, further described in next subsections: •...
Page 566 AES hardware accelerator (AES) RM0461 GCM payload phase This phase, identical for encryption and decryption, is executed after the GCM header phase. During this phase, the encrypted/decrypted payload is stored in the AES_DOUTR register. The sequence to execute is: Indicate the payload phase, by setting to 10 the GCMPH[1:0] bitfield of the AES_CR register.
Page 567 RM0461 AES hardware accelerator (AES) Suspend/resume operations in GCM mode To suspend the processing of a message, proceed as follows: If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN bit of the AES_CR register. If DMA is not used, make sure that the current computation is completed, which is indicated by the CCF flag of the AES_SR register set to 1.
Page 568: Figure 106. Message Construction In Gmac Mode
AES hardware accelerator (AES) RM0461 A typical message construction for GMAC is given in Figure 106. Figure 106. Message construction in GMAC mode [Len(A)] Len(A) 16-byte boundaries Last Authenticated data block 4-byte boundaries Authentication tag (T) Initialization vector (IV) Counter Zero padding MSv42158V2 AES GMAC processing...
Page 569: Figure 108. Message Construction In Ccm Mode
RM0461 AES hardware accelerator (AES) Suspend/resume operations in GMAC In GMAC mode, the sequence described for the GCM applies except that only the header phase can be interrupted. 21.4.12 AES counter with CBC-MAC (CCM) Overview The AES counter with cipher block chaining-message authentication code (CCM) algorithm allows encryption and authentication of plaintext, generating the corresponding ciphertext and tag (also known as message authentication code).
Page 570 AES hardware accelerator (AES) RM0461 known length Len(A) that can be a non-multiple of 16 bytes (see Figure 108). The standard also states that, on MSB bits of the first message block (B1), the associated data length expressed in bytes (a) must be encoded as follows: –...
Page 571: Table 125. Initialization Of Aes_Ivrx Registers In Ccm Mode
RM0461 AES hardware accelerator (AES) CCM processing Figure 109 describes the CCM implementation within the AES peripheral (encryption example). This mode is selected by writing 100 into the CHMOD[2:0] bitfield of the AES_CR register. Figure 109. CCM mode authenticated encryption Block 1 Block m (3) Payload...
Page 572 AES hardware accelerator (AES) RM0461 Note: In this mode, the setting 01 of the MODE[1:0] bitfield (key derivation) is forbidden. A CCM message is processed through the following phases, further described in next subsections: • Init phase: AES processes the first block and prepares the first counter block. •...
Page 573 RM0461 AES hardware accelerator (AES) CCM payload phase (encryption or decryption) This phase, identical for encryption and decryption, is executed after the CCM header phase. During this phase, the encrypted/decrypted payload is stored in the AES_DOUTR register. The sequence to execute is: Indicate the payload phase, by setting to 10 the GCMPH[1:0] bitfield of the AES_CR register.
Page 574 AES hardware accelerator (AES) RM0461 AES_SR register then stop the DMA transfers from the OUT FIFO by clearing the DMAOUTEN bit of the AES_CR register. Clear the CCF flag of the AES_SR register, by setting to 1 the CCFC bit of the AES_CR register.
Page 575: Figure 110. 128-Bit Block Construction With Respect To Data Swap
RM0461 AES hardware accelerator (AES) Data swapping The AES peripheral can be configured to perform a bit-, a byte-, a half-word-, or no swapping on the input data word in the AES_DINR register, before loading it to the AES processing core, and on the data output from the AES processing core, before sending it to the AES_DOUTR register.
Page 576: Table 126. Key Endianness In Aes_Keyrx Registers (128- Or 256-Bit Key Length)
AES hardware accelerator (AES) RM0461 Note: The data in AES key registers (AES_KEYRx) and initialization registers (AES_IVRx) are not sensitive to the swap mode selection. Data padding Figure 110 also gives an example of memory data block padding with zeros such that the zeroed bits after the data swap form a contiguous zone at the MSB end of the AES core input buffer.
Page 577: Figure 111. Dma Transfer Of A 128-Bit Data Block During Input Phase
RM0461 AES hardware accelerator (AES) 21.4.16 AES DMA interface The AES peripheral provides an interface to connect to the DMA (direct memory access) controller. The DMA operation is controlled through the AES_CR register. Data input using DMA Setting the DMAINEN bit of the AES_CR register enables DMA writing into AES. The AES peripheral then initiates a DMA request during the input phase each time it requires to write a 128-bit block (quadruple word) to the AES_DINR register, as shown in Figure...
Page 578: Figure 112. Dma Transfer Of A 128-Bit Data Block During Output Phase
AES hardware accelerator (AES) RM0461 Figure 112. DMA transfer of a 128-bit data block during output phase Chronological order Increasing address Memory accessed through DMA Word3 Word2 Word1 Word0 DOUT[127:96] DOUT[95:64] DOUT[63:32] DOUT[31:0] D127 DMA req N DMA req N+1 DMA req N+2 DMA req N+3 single read...
Page 579: Table 127. Aes Interrupt Requests
RM0461 AES hardware accelerator (AES) Note: AES is not disabled after a WRERR error detection and continues processing. An interrupt is generated if the ERRIE bit of the AES_CR register is set. For more details, refer to Section 21.5: AES interrupts.
Page 580: Table 129. Processing Latency For Gcm And Ccm (In Clock Cycles)
AES hardware accelerator (AES) RM0461 Table 129. Processing latency for GCM and CCM (in clock cycles) Header Payload Key size Mode of operation Algorithm Init Phase Tag phase phase phase Mode 1: Encryption/ 128-bit Mode 3: Decryption Mode 1: Encryption/ 256-bit Mode 3: Decryption 1.
Page 581 RM0461 AES hardware accelerator (AES) Bits 14:13 GCMPH[1:0]: GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: 00: Init phase 01: Header phase 10: Payload phase 11: Final phase The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield).
Page 582 AES hardware accelerator (AES) RM0461 Bits 16, 6:5 CHMOD[2:0]: Chaining mode selection This bitfield selects the AES chaining mode: 000: Electronic codebook (ECB) 001: Cipher-block chaining (CBC) 010: Counter mode (CTR) 011: Galois counter mode (GCM) and Galois message authentication code (GMAC) 100: Counter with CBC-MAC (CCM) others: Reserved Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the...
Page 583 RM0461 AES hardware accelerator (AES) Bit 3 BUSY: Busy This flag indicates whether AES is idle or busy during GCM payload encryption phase: 0: Idle 1: Busy When the flag indicates “idle”, the current GCM encryption processing may be suspended to process a higher-priority message.
Page 584 AES hardware accelerator (AES) RM0461 21.7.3 AES data input register (AES_DINR) Address offset: 0x08 Reset value: 0x0000 0000 Only 32-bit access type is supported. DIN[31:16] DIN[15:0] Bits 31:0 DIN[31:0]: Input data word A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the AES peripheral.
Page 585 RM0461 AES hardware accelerator (AES) Bits 31:0 DOUT[31:0]: Output data word This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the AES peripheral.
Page 586 AES hardware accelerator (AES) RM0461 Bits 31:0 KEY[63:32]: Cryptographic key, bits [63:32] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield. 21.7.7 AES key register 2 (AES_KEYR2) Address offset: 0x18 Reset value: 0x0000 0000 KEY[95:80] KEY[79:64] Bits 31:0 KEY[95:64]: Cryptographic key, bits [95:64] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
Page 587 RM0461 AES hardware accelerator (AES) Bits 31:0 IVI[31:0]: Initialization vector input, bits [31:0] Refer to Section 21.4.15: AES initialization vector registers on page 576 for description of the IVI[127:0] bitfield. The initialization vector is only used in chaining modes other than ECB. The AES_IVRx registers may be written only when the AES peripheral is disabled 21.7.10 AES initialization vector register 1 (AES_IVR1)
Page 588 AES hardware accelerator (AES) RM0461 Bits 31:0 IVI[127:96]: Initialization vector input, bits [127:96] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield. 21.7.13 AES key register 4 (AES_KEYR4) Address offset: 0x30 Reset value: 0x0000 0000 KEY[159:144] KEY[143:128] Bits 31:0 KEY[159:128]: Cryptographic key, bits [159:128] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
Page 589 RM0461 AES hardware accelerator (AES) 21.7.16 AES key register 7 (AES_KEYR7) Address offset: 0x3C Reset value: 0x0000 0000 KEY[255:240] KEY[239:224] Bits 31:0 KEY[255:224]: Cryptographic key, bits [255:224] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield. Note: The key registers from 4 to 7 are used only when the key length of 256 bits is selected. They have no effect when the key length of 128 bits is selected (only key registers 0 to 3 are used in that case).
Page 590: Table 130. Aes Register Map And Reset Values
AES hardware accelerator (AES) RM0461 21.7.18 AES register map Table 130. AES register map and reset values Offset Register AES_CR 0x000 Reset value AES_SR 0x004 Reset value AES_DINR DIN[31:0] 0x008 Reset value AES_DOUTR DOUT[31:0] 0x00C Reset value AES_KEYR0 KEY[31:0] 0x010 Reset value AES_KEYR1 KEY[63:32]...
Page 591 RM0461 AES hardware accelerator (AES) Table 130. AES register map and reset values (continued) Offset Register AES_SUSP1R SUSP[31:0] 0x044 Reset value AES_SUSP2R SUSP[31:0] 0x048 Reset value AES_SUSP3R SUSP[31:0] 0x04C Reset value AES_SUSP4R SUSP[31:0] 0x050 Reset value AES_SUSP5R SUSP[31:0] 0x054 Reset value AES_SUSP6R SUSP[31:0] 0x058...
Page 592 Public key accelerator (PKA) RM0461 Public key accelerator (PKA) 22.1 Introduction PKA (public key accelerator) is intended for the computation of cryptographic public key primitives, specifically those related to RSA, Diffie-Hellmann or ECC (elliptic curve cryptography) over GF(p) (Galois fields). To achieve high performance at a reasonable cost, these operations are executed in the Montgomery domain.
Page 593: Table 131. Internal Input/Output Signals
RM0461 Public key accelerator (PKA) Figure 113. PKA block diagram Banked registers (main) PKA32 PKA_CR control PKA_SR status interface PKA_CLRFR clear 894x32-bit PKA RAM pka_hclk 32-bit Control PKA core pka_it interface logic MS45419V1 22.3.2 PKA internal signals Table 131 lists internal signals available at the IP level, not necessarily available on product bonding pads.
Page 594: Table 132. Pka Integer Arithmetic Functions List
Public key accelerator (PKA) RM0461 PKA operating modes The list of operations the PKA can perform is detailed in Table 132 Table 133, respectively, for integer arithmetic functions and prime field (Fp) elliptic curve functions. Each of these operating modes has an associated code that has to be written to the MODE field in the PKA_CR register.
Page 595 RM0461 Public key accelerator (PKA) supplied before starting the operation. Performance improvement is detailed in Section 22.5.2: Computation times. The operations using fast mode are modular exponentiation and scalar multiplication. 22.3.5 Typical applications for PKA Introduction The PKA can be used to accelerate a number of public key cryptographic functions. In particular: •...
Page 596 Public key accelerator (PKA) RM0461 Alice, to decrypt ciphertext c using her private key, follows the steps indicated below: Convert the ciphertext C to an integer ciphertext representative c. Recover plaintext m = c mod n = (m mod n. If the private key is the quintuple (p, q, dp, dq, qInv), then plaintext m is obtained by performing the operations: mod p mod q...
Page 597 RM0461 Public key accelerator (PKA) ECDSA signature verification ECDSA (elliptic curve digital signature algorithm) signature verification function principle is the following: Bob, to authenticate Alice's signature, must have a copy of her public key curve point Q Bob can verify that Q is a valid curve point going through the following steps: check that Q is not equal to the identity element O...
Page 598 Public key accelerator (PKA) RM0461 Using precomputed Montgomery parameters (PKA fast mode) As explained in Section 22.3.4, when computing many operations with the same modulus it can be beneficial for the application to compute only once the corresponding Montgomery parameter (see, for example, Section 22.4.5).
Page 599: Table 134. Montgomery Parameter Computation
RM0461 Public key accelerator (PKA) Note: Fractional results for above formulas are rounded up to the nearest integer since PKA core processes 32-bit words. Note: The maximum ROS is 99 words (3136-bit max exponent size), while the maximum EOS is 21 words (640-bit max operand size).
Page 600: Table 135. Modular Addition
Public key accelerator (PKA) RM0461 22.4.3 Modular addition Modular addition operation consists in the computation of A + B mod n. Operation instructions are summarized in Table 135. Table 135. Modular addition Parameters with direction Value (Note) Storage Size MODE 0x0E PKA_CR 6 bits...
Page 601: Table 137. Montgomery Multiplication
RM0461 Public key accelerator (PKA) Inward (or outward) conversion into (or from) Montgomery domain Let’s assume A is an integer in the natural domain Compute r2modn using Montgomery parameter computation Result AR= A x r2modn mod n is A in the Montgomery domain Let’s assume BR is an integer in the Montgomery domain Result B = BR x 1 mod n is B in the natural domain Similarly, above value AR computed in a) can be converted into the natural...
Page 602: Table 138. Modular Exponentiation (Normal Mode)
Public key accelerator (PKA) RM0461 Table 138. Modular exponentiation (normal mode) Parameters with direction Value (Note) Storage Size MODE 0x00 PKA_CR 6 bits Exponent length (in bits, not null) RAM@0x400 32 bits Operand length (in bits, not null) RAM@0x404 Operand A (base of IN/OUT (0 ≤...
Page 603: Table 141. Modular Reduction
RM0461 Public key accelerator (PKA) 22.4.8 Modular reduction Modular reduction operation consists in the computation of the remainder of A divided by n. Operation instructions are summarized in Table 141. Table 141. Modular reduction Parameters with direction Value (Note) Storage Size MODE 0x0D...
Page 604: Table 144. Arithmetic Multiplication
Public key accelerator (PKA) RM0461 22.4.11 Arithmetic multiplication Arithmetic multiplication operation consists in the computation of AxB. Operation instructions are summarized in Table 144. Table 144. Arithmetic multiplication Parameters with direction Value (Note) Storage Size MODE 0x0B PKA_CR 6 bits Operand length M (In bits, not null) RAM@0x404...
Page 605: Table 146. Crt Exponentiation
RM0461 Public key accelerator (PKA) These values allow the recipient to compute the exponentiation m = A (mod pq) more efficiently as follows: • mod p • mod p • h = q ) mod p, with m > m •...
Page 606: Table 147. Point On Elliptic Curve Fp Check
Public key accelerator (PKA) RM0461 Table 147. Point on elliptic curve Fp check Parameters with direction Value (Note) Storage Size MODE 0x28 PKA_CR 6 bits (In bits, not null, Modulus length RAM@0x404 8 < value < 640) 32 bits 0x0: positive Curve coefficient a sign RAM@0x408 0x1: negative...
Page 607: Table 149. Ecc Fp Scalar Multiplication (Fast Mode)
RM0461 Public key accelerator (PKA) Table 149. ECC Fp scalar multiplication (Fast Mode) Parameters with direction Value (Note) Storage Size MODE 0x22 PKA_CR 6 bits (In bits, not null, Scalar multiplier k length RAM@0x400 8 < value < 640) (In bits, not null, Modulus length RAM@0x404 32 bits...
Page 608: Table 150. Ecdsa Sign - Inputs
Public key accelerator (PKA) RM0461 Table 150. ECDSA sign - Inputs Parameters with direction Value (Note) Storage Size MODE 0x24 PKA_CR 6 bits Curve prime order n (in bits, not null) RAM@0x400 length Curve modulus p length (in bits, 8 < value < 640) RAM@0x404 32 bits 0x0: positive...
Page 609: Table 152. Extended Ecdsa Sign (Extra Outputs)
RM0461 Public key accelerator (PKA) Table 152. Extended ECDSA sign (extra outputs) Parameters with direction Value (Note) Storage Size Curve point kG coordinate x (0 ≤ x < p) RAM@0x103C Curve point kG coordinate y (0 ≤ y < p) RAM@0x1090 22.4.17 ECDSA verification...
Page 610: Table 155. Family Of Supported Curves For Ecc Operations
Public key accelerator (PKA) RM0461 22.5 Example of configurations and processing times 22.5.1 Supported elliptic curves The PKA supports all non-singular elliptic curves defined over prime fields. Those curvescan be described with a short Weierstrass equation y + ax + b (mod p). Note: Binary curves, Edwards curves and Curve25519 are not supported by the PKA.
Page 611 RM0461 Public key accelerator (PKA) Table 155. Family of supported curves for ECC operations (continued) Curve name Standard Reference brainpoolP224r1, brainpoolP224t1 brainpoolP256r1, brainpoolP256t1 – Brainpool Elliptic Curves, IETF RFC 5639 brainpoolP320r1, – Brainpool Elliptic Curves for the Internet Key IETF https://tools.ietf.org brainpoolP320t1 Exchange (IKE) Group Description Registry, IETF...
Page 612: Table 156. Modular Exponentiation Computation Times
Public key accelerator (PKA) RM0461 22.5.2 Computation times The following tables summarize the PKA computation times, expressed in clock cycles. Table 156. Modular exponentiation computation times Modulus length (in bits) Exponent length Mode (in bits) 1024 2048 3072 Normal 304000 814000 1728000 Fast...
Page 613: Table 159. Ecdsa Verification Average Computation Times
RM0461 Public key accelerator (PKA) Table 159. ECDSA verification average computation times Modulus length (in bits) 3500000 5350000 10498000 18126000 29118000 61346000 71588000 Table 160. Point on elliptic curve Fp check average computation times Modulus length (in bits) 10800 14200 20400 31000 49600...
Page 614 Public key accelerator (PKA) RM0461 22.7 PKA registers 22.7.1 PKA control register (PKA_CR) Address offset: 0x00 Reset value: 0x0000 0000 ADDR PROC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ERRIE ERRIE ENDIE Res. Res. MODE[5:0] Res.
Page 615 RM0461 Public key accelerator (PKA) Bits 7:2 Reserved, must be kept at reset value. Bit 1 START: start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. Note: START is ignored if PKA is busy.
Page 616 Public key accelerator (PKA) RM0461 22.7.3 PKA clear flag register (PKA_CLRFR) Address offset: 0x08 Reset value: 0x0000 0000 ADDR PROC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ERRFC ERRFC ENDFC Res. Res. Res. Res. Res.
Page 617: Table 163. Pka Register Map And Reset Values
RM0461 Public key accelerator (PKA) 22.7.5 PKA register map Table 163. PKA register map and reset values Register Offset name PKA_CR MODE[5:0] 0x000 Reset value PKA_SR 0x004 Reset value PKA_CLRFR 0x008 Reset value Refer to Section 2.4 on page 62 for the register boundary addresses.
Page 618 Advanced-control timer (TIM1) RM0461 Advanced-control timer (TIM1) In this section, “TIMx” should be understood as “TIM1” since there is only one instance of this type of timer for the products to which this reference manual applies. 23.1 TIM1 introduction The advanced-control timer (TIM1) consists of a 16-bit auto-reload counter driven by a programmable prescaler.
Page 619 RM0461 Advanced-control timer (TIM1) 23.2 TIM1 main features TIM1 timer features include: • 16-bit up, down, up/down auto-reload counter. • 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65536. •...
Page 620: Figure 114. Advanced-Control Timer Block Diagram
Advanced-control timer (TIM1) RM0461 Figure 114. Advanced-control timer block diagram Internal clock (CK_INT) from RCC Trigger ETRF TRGO controller ETRP TIMx_ETR to other timers Polarity selection & Input to peripherals edgedetector & prescaler filter On-chip ETR ITR[0..15] sources Slave Reset, enable, up/down, count TRGI controller mode...
Page 621 RM0461 Advanced-control timer (TIM1) 23.3 TIM1 functional description 23.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 622: Figure 115. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Advanced-control timer (TIM1) RM0461 Figure 115. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 116.
Page 623 RM0461 Advanced-control timer (TIM1) 23.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1.
Page 624: Figure 117. Counter Timing Diagram, Internal Clock Divided By 1
Advanced-control timer (TIM1) RM0461 Figure 117. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT 34 35 36 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31078V2 Figure 118. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 625: Figure 119. Counter Timing Diagram, Internal Clock Divided By 4
RM0461 Advanced-control timer (TIM1) Figure 119. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31080V2 Figure 120. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register...
Page 626: Figure 121. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded)
Advanced-control timer (TIM1) RM0461 Figure 121. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31082V3 Figure 122.
Page 627 RM0461 Advanced-control timer (TIM1) Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1.
Page 628: Figure 123. Counter Timing Diagram, Internal Clock Divided By 1
Advanced-control timer (TIM1) RM0461 Figure 123. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT 03 02 01 00 34 33 32 Counter register Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) MS31184V1 Figure 124. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 629: Figure 125. Counter Timing Diagram, Internal Clock Divided By 4
RM0461 Advanced-control timer (TIM1) Figure 125. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0001 0000 0000 0001 Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31186V1 Figure 126. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register...
Page 630: Figure 127. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
Advanced-control timer (TIM1) RM0461 Figure 127. Counter timing diagram, update event when repetition counter is not used CK_PSC Timerclock = CK_CNT 30 2F Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31188V1 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the...
Page 631: Figure 128. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
RM0461 Advanced-control timer (TIM1) DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 632: Figure 129. Counter Timing Diagram, Internal Clock Divided By 2
Advanced-control timer (TIM1) RM0461 Figure 129. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0001 0000 0001 0002 0003 0003 0002 Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31190V1 Figure 130. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 633: Figure 131. Counter Timing Diagram, Internal Clock Divided By N
RM0461 Advanced-control timer (TIM1) Figure 131. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31192V1 Figure 132. Counter timing diagram, update event with ARPE=1 (counter underflow) CK_PSC Timerclock = CK_CNT 05 04 03 02...
Page 634: Figure 133. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow)
Advanced-control timer (TIM1) RM0461 Figure 133. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_PSC Timer clock = CK_CNT Counter register F8 F9 FA FB FC 31 30 2F Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active...
Page 635: Figure 134. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
RM0461 Advanced-control timer (TIM1) In Center aligned mode, for odd values of RCR, the update event occurs either on the overflow or on the underflow depending on when the RCR register was written and when the counter was launched: if the RCR was written before launching the counter, the UEV occurs on the underflow.
Page 636: Figure 135. External Trigger Input Block
Advanced-control timer (TIM1) RM0461 23.3.4 External trigger input The timer features an external trigger input ETR. It can be used as: • external clock (external clock mode 2, see Section 23.3.5) • trigger for the slave mode (see Section 23.3.26) •...
Page 637: Figure 137. Control Circuit In Normal Mode, Internal Clock Divided By 1
RM0461 Advanced-control timer (TIM1) 23.3.5 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Encoder mode Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed...
Page 638: Figure 138. Ti2 External Clock Connection Example
Advanced-control timer (TIM1) RM0461 Figure 138. TI2 external clock connection example TIMx_SMCR TS[4:0] TI2F TI1F Encoder mode ITRx 000xx TIMx_CH2 TI1_ED TRGI External clock 00100 mode 1 CK_PSC TI1FP1 TI2[0] 00101 TI2F_Rising Edge External clock TI2FP2 ETRF 00110 Filter TI2[1..15] detector mode 2 ETRF...
Page 639: Figure 139. Control Circuit In External Clock Mode 1
RM0461 Advanced-control timer (TIM1) Figure 139. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 MS31087V2 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR.
Page 640: Figure 141. Control Circuit In External Clock Mode 2
Advanced-control timer (TIM1) RM0461 As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 641: Figure 142. Capture/Compare Channel (Example: Channel 1 Input Stage)
RM0461 Advanced-control timer (TIM1) 23.3.6 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), an input stage for capture (with digital filter, multiplexing, and prescaler, except for channels 5 and 6) and an output stage (with comparator and output control). Figure 142 Figure 145 give an overview of one Capture/Compare channel.
Page 642: Figure 144. Output Stage Of Capture/Compare Channel (Channel 1, Idem Ch. 2 And 3)
Advanced-control timer (TIM1) RM0461 Figure 144. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) TIMx_SMCR OCCS OCREF_CLR To the master mode controller ETRF Output enable ‘0’ circuit ocref_clr_int OC1REF OC1REFC OC1_DT CC1P CNT>CCR1 Output Output Dead-time TIM1_CCER mode CNT=CCR1...
Page 643: Figure 146. Output Stage Of Capture/Compare Channel (Channel 5, Idem Ch. 6)
RM0461 Advanced-control timer (TIM1) Figure 146. Output stage of capture/compare channel (channel 5, idem ch. 6) TIMx_SMCR OCCS To the master OCREF_CLR mode controller ETRF ocref_clr_int ‘0’ Output CNT > CCR5 Output enable OC5REF mode circuit CNT = CCR5 controller CC5E CC5P CC5E TIM1_CCER...
Page 644 Advanced-control timer (TIM1) RM0461 detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NP bits to 0 in the TIMx_CCER register (rising edge in this case). Program the input prescaler.
Page 645: Figure 147. Pwm Input Mode Timing
RM0461 Advanced-control timer (TIM1) Select the proper TI1x source (internal or external) with the TI1SEL[3:0] bits in the TIMx_TISEL register. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P and CC1NP bits to ‘0’...
Page 646 Advanced-control timer (TIM1) RM0461 23.3.10 Output compare mode This function is used to control an output waveform or indicate when a period of time has elapsed. Channels 1 to 4 can be output, while Channel 5 and 6 are only available inside the device (for instance, for compound waveform generation or for ADC triggering).
Page 647: Figure 148. Output Compare Mode, Toggle On Oc1
RM0461 Advanced-control timer (TIM1) Figure 148. Output compare mode, toggle on OC1 Write B201h in the CC1R register 0039 003A 003B B200 B201 TIM1_CNT B201 003A TIM1_CCR1 OC1REF= OC1 Match detected on CCR1 Interrupt generated if enabled MS31092V1 23.3.11 PWM mode Pulse Width Modulation mode allows a signal to be generated with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 648: Figure 149. Edge-Aligned Pwm Waveforms (Arr=8)
Advanced-control timer (TIM1) RM0461 PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 623. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <...
Page 649: Figure 150. Center-Aligned Pwm Waveforms (Arr=8)
RM0461 Advanced-control timer (TIM1) TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting) on page 630. Figure 150 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, •...
Page 650 Advanced-control timer (TIM1) RM0461 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
Page 651: Figure 151. Generation Of 2 Phase-Shifted Pwm Signals With 50% Duty Cycle
RM0461 Advanced-control timer (TIM1) Figure 151. Generation of 2 phase-shifted PWM signals with 50% duty cycle Counter register OC1REFC CCR1=0 CCR2=8 OC3REFC CCR3=3 CCR4=5 MS33117V1 23.3.13 Combined PWM mode Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses.
Page 652: Figure 152. Combined Pwm Mode On Channel 1 And 3
Advanced-control timer (TIM1) RM0461 Figure 152. Combined PWM mode on channel 1 and 3 OC2’ OC1’ OC1REF OC2REF OC1REF’ OC2REF’ OC1REFC OC1REFC’ OC1REFC = OC1REF AND OC2REF OC1REFC’ = OC1REF’ OR OC2REF’ MS31094V1 23.3.14 Combined 3-phase PWM mode Combined 3-phase PWM mode allows one to three center-aligned PWM signals to be generated with a single programmable signal ANDed in the middle of the pulses.
Page 653: Figure 153. 3-Phase Combined Pwm Signals With Multiple Trigger Pulses Per Period
RM0461 Advanced-control timer (TIM1) Figure 153. 3-phase combined PWM signals with multiple trigger pulses per period Counter OC5ref OC1refC OC2refC OC3refC Preload Active OC4ref OC6ref TRGO2 MS33102V1 The TRGO2 waveform shows how the ADC can be synchronized on given 3-phase PWM signals.
Page 654: Figure 154. Complementary Output With Dead-Time Insertion
Advanced-control timer (TIM1) RM0461 Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: •...
Page 655: Figure 156. Dead-Time Waveforms With Delay Greater Than The Positive Pulse
RM0461 Advanced-control timer (TIM1) Figure 156. Dead-time waveforms with delay greater than the positive pulse OCxREF OCxN delay MS31097V1 The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 23.4.20: TIM1 break and dead-time register (TIM1_BDTR) for delay calculation.
Page 656 Advanced-control timer (TIM1) RM0461 The output enable signal and output levels during break are depending on several control bits: – the MOE bit in TIMx_BDTR register allows the outputs to be enabled/disabled by software and is reset in case of break or break2 event. –...
Page 657: Figure 157. Break And Break2 Circuitry Overview
RM0461 Advanced-control timer (TIM1) All sources are ORed before entering the timer BRK or BRK2 inputs, as per Figure 157 below. Figure 157. Break and Break2 circuitry overview Lockup LOCK Core Lockup PVD LOCK System break requests SBIF flag Parity LOCK RAM parity Error ECC LOCK Double ECC Error...
Page 658 Advanced-control timer (TIM1) RM0461 When one of the breaks occurs (selected level on one of the break inputs): • The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or even releasing the control to the GPIO controller (selected by the OSSI bit). This feature is enabled even if the MCU oscillator is off.
Page 659: Figure 158. Various Output Behavior In Response To A Break Event On Brk (Ossi = 1)
RM0461 Advanced-control timer (TIM1) Figure 158. Various output behavior in response to a break event on BRK (OSSI = 1) BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay...
Page 660: Table 164. Behavior Of Timer Outputs Versus Brk/Brk2 Inputs
Advanced-control timer (TIM1) RM0461 The two break inputs have different behaviors on timer outputs: – The BRK input can either disable (inactive state) or force the PWM outputs to a predefined safe state. – BRK2 can only disable (inactive state) the PWM outputs. The BRK has a higher priority than BRK2 input, as described in Table 164.
Page 661: Figure 160. Pwm Output State Following Brk Assertion (Ossi=0)
RM0461 Advanced-control timer (TIM1) Figure 160. PWM output state following BRK assertion (OSSI=0) I/O state defined by the GPIO controller (HI-Z) Deadtime I/O state I/O state defined by the GPIO controller (HI-Z) Active Inactive Disabled MS34107V1 23.3.17 Bidirectional break inputs The TIM1 are featuring bidirectional break I/Os, as represented on Figure 161.
Page 662: Table 165. Break Protection Disarming Conditions
Advanced-control timer (TIM1) RM0461 Table 165. Break protection disarming conditions BKDIR BKDSRM Break protection state (BK2DIR) (BK2DSRM) Armed Armed Disarmed Armed Arming and re-arming break circuitry The break circuitry (in input or bidirectional mode) is armed by default (peripheral reset configuration).
Page 663: Figure 162. Clearing Timx Ocxref
RM0461 Advanced-control timer (TIM1) 23.3.18 Clearing the OCxREF signal on an external event The OCxREF signal of a given channel can be cleared when a high level is applied on the ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1). OCxREF remains low until the next update event (UEV) occurs.
Page 664: Figure 163. 6-Step Generation, Com Example (Ossr=1)
Advanced-control timer (TIM1) RM0461 23.3.19 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus one can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 665: Figure 164. Example Of One Pulse Mode
RM0461 Advanced-control timer (TIM1) 23.3.20 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 666 Advanced-control timer (TIM1) RM0461 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 667: Figure 165. Retriggerable One Pulse Mode
RM0461 Advanced-control timer (TIM1) Figure 165. Retriggerable one pulse mode TRGI Counter Output MS33106V1 23.3.22 Encoder interface mode To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and SMS=’011’...
Page 668: Table 166. Counting Direction Versus Encoder Signals
Advanced-control timer (TIM1) RM0461 Table 166. Counting direction versus encoder signals Level on TI1FP1 signal TI2FP2 signal opposite signal (TI1FP1 Active edge for TI2, Rising Falling Rising Falling TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count No Count...
Page 669: Figure 167. Example Of Encoder Interface Mode With Ti1Fp1 Polarity Inverted
RM0461 Advanced-control timer (TIM1) Figure 167 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 167. Example of encoder interface mode with TI1FP1 polarity inverted. forward jitter backward jitter forward Counter down down MS33108V1...
Page 670: Figure 168. Measuring Time Interval Between Edges On 3 Signals
Advanced-control timer (TIM1) RM0461 23.3.24 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of an XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3.
Page 671 RM0461 Advanced-control timer (TIM1) Example: one wants to change the PWM configuration of the advanced-control timer TIM1 after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers. • Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the TIMx_CR2 register to ‘1’, •...
Page 672: Figure 169. Example Of Hall Sensor Interface
Advanced-control timer (TIM1) RM0461 Figure 169. Example of Hall sensor interface TIH1 TIH2 TIH3 Counter (CNT) (CCR2) CCR1 C7A3 C7A8 C794 C7A5 C7AB C796 TRGO=OC2REF OC1N OC2N OC3N Write CCxE, CCxNE and OCxM for next step MS32672V1 672/1306 RM0461 Rev 5...
Page 673: Figure 170. Control Circuit In Reset Mode
RM0461 Advanced-control timer (TIM1) 23.3.26 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. Refer to Section 24.3.19: Timer synchronization for details. They can be synchronized in several modes: Reset mode, Gated mode, and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Page 674: Figure 171. Control Circuit In Gated Mode
Advanced-control timer (TIM1) RM0461 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000).
Page 675: Figure 172. Control Circuit In Trigger Mode
RM0461 Advanced-control timer (TIM1) register. Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). • Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=00110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
Page 676: Figure 173. Control Circuit In External Clock Mode 2 + Trigger Mode
Advanced-control timer (TIM1) RM0461 In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs: Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: –...
Page 677 RM0461 Advanced-control timer (TIM1) 23.3.27 ADC synchronization The timer can generate an ADC triggering event with various internal signals, such as reset, enable or compare events. It is also possible to generate a pulse issued by internal edge detectors, such as: –...
Page 678 Advanced-control timer (TIM1) RM0461 This is done in the following steps: Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers.
Page 679 RM0461 Advanced-control timer (TIM1) 23.4 TIM1 registers Refer to for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 23.4.1 TIM1 control register 1 (TIM1_CR1) Address offset: 0x00 Reset value: 0x0000 UIFRE Res.
Page 680 Advanced-control timer (TIM1) RM0461 Bit 4 DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source...
Page 681 RM0461 Advanced-control timer (TIM1) Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 MMS2[3:0]: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: 0000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2).
Page 682 Advanced-control timer (TIM1) RM0461 Bit 12 OIS3: Output Idle state 3 (OC3 output) Refer to OIS1 bit Bit 11 OIS2N: Output Idle state 2 (OC2N output) Refer to OIS1N bit Bit 10 OIS2: Output Idle state 2 (OC2 output) Refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0...
Page 683 RM0461 Advanced-control timer (TIM1) Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI Note: This bit acts only on channels that have a complementary output.
Page 684 Advanced-control timer (TIM1) RM0461 Bits 13:12 ETPS[1:0]: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of f frequency. A CK_INT prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
Page 685: Table 167. Tim1 Internal Trigger Connection
RM0461 Advanced-control timer (TIM1) Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 686 Advanced-control timer (TIM1) RM0461 Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bit 13 COMDE: COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled...
Page 687 RM0461 Advanced-control timer (TIM1) Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 23.4.5...
Page 688 Advanced-control timer (TIM1) RM0461 Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bit 8 B2IF: Break 2 interrupt flag...
Page 689 RM0461 Advanced-control timer (TIM1) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...
Page 690 Advanced-control timer (TIM1) RM0461 Bit 2 CC2G: Capture/Compare 2 generation Refer to CC1G description Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
Page 691 RM0461 Advanced-control timer (TIM1) Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC.
Page 692 Advanced-control timer (TIM1) RM0461 corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Output compare mode: Res.
Page 693 RM0461 Advanced-control timer (TIM1) Bits 16, 6:4 OC1M[3:0]: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 694 Advanced-control timer (TIM1) RM0461 Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 695 RM0461 Advanced-control timer (TIM1) Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 IC4F[3:0]: Input capture 4 filter Refer to IC1F[3:0] description. Bits 11:10 IC4PSC[1:0]: Input capture 4 prescaler Refer to IC1PSC[1:0] description. Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input.
Page 696 Advanced-control timer (TIM1) RM0461 Bits 31:25 Reserved, must be kept at reset value. Bits 23:17 Reserved, must be kept at reset value. Bit 15 OC4CE: Output compare 4 clear enable Refer to OC1CE description. Bits 24, 14:12 OC4M[3:0]: Output compare 4 mode Refer to OC3M[3:0] description.
Page 697 RM0461 Advanced-control timer (TIM1) 23.4.11 TIM1 capture/compare enable register (TIM1_CCER) Address offset: 0x20 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC6P CC6E Res. Res. CC5P CC5E CC4NP Res. CC4P CC4E CC3NP CC3NE CC3P CC3E CC2NP CC2NE CC2P...
Page 698 Advanced-control timer (TIM1) RM0461 Bit 5 CC2P: Capture/Compare 2 output polarity Refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable Refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high. 1: OC1N active low.
Page 699: Table 168. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
RM0461 Advanced-control timer (TIM1) Bit 0 CC1E: Capture/Compare 1 output enable 0: Capture mode disabled / OC1 is not active (see below) 1: Capture mode enabled / OC1 signal is output on the corresponding output pin When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state.
Page 700 Advanced-control timer (TIM1) RM0461 23.4.12 TIM1 counter (TIM1_CNT) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNT[15:0] Bit 31 UIFCPY: UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.
Page 701 RM0461 Advanced-control timer (TIM1) 23.4.15 TIM1 repetition counter register (TIM1_RCR) Address offset: 0x30 Reset value: 0x0000 REP[15:0] Bits 15:0 REP[15:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Page 702 Advanced-control timer (TIM1) RM0461 23.4.17 TIM1 capture/compare register 2 (TIM1_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
Page 703 RM0461 Advanced-control timer (TIM1) 23.4.19 TIM1 capture/compare register 4 (TIM1_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE).
Page 704 Advanced-control timer (TIM1) RM0461 Bit 28 BKBID: Break Bidirectional 0: Break input BRK in input mode 1: Break input BRK in bidirectional mode In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode.
Page 705 RM0461 Advanced-control timer (TIM1) Bits 23:20 BK2F[3:0]: Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK2 acts asynchronously 0001: f...
Page 706 Advanced-control timer (TIM1) RM0461 Bit 15 MOE: Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output.
Page 707 RM0461 Advanced-control timer (TIM1) Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (Section 23.4.11: TIM1 capture/compare enable register (TIM1_CCER)).
Page 708 Advanced-control timer (TIM1) RM0461 Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers.
Page 709 RM0461 Advanced-control timer (TIM1) Bits 31:0 DMAB[31:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
Page 710 Advanced-control timer (TIM1) RM0461 Res. Res. Res. Res. Res. Res. Res. OC6M[3] Res. Res. Res. Res. Res. Res. Res. OC5M[3] OC6M[2:0] OC6FE Res. Res. OC5M[2:0] OC5PE OC5FE Res. Res. Bits 31:25 Reserved, must be kept at reset value. Bits 23:17 Reserved, must be kept at reset value. Bit 15 OC6CE: Output compare 6 clear enable Refer to OC1CE description.
Page 711 RM0461 Advanced-control timer (TIM1) Bit 31 GC5C3: Group Channel 5 and Channel 3 Distortion on Channel 3 output: 0: No effect of OC5REF on OC3REFC 1: OC3REFC is the logical AND of OC3REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2).
Page 712 Advanced-control timer (TIM1) RM0461 23.4.27 TIM1 alternate function option register 1 (TIM1_AF1) Address offset: 0x60 Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETRSEL[3:2] ETRSEL[1:0] Res. Res. BKINP Res. Res. Res.
Page 713 RM0461 Advanced-control timer (TIM1) Bit 2 BKCMP2E: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is ‘ORed’ with the other BRK sources. 0: COMP2 input disabled 1: COMP2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 714 Advanced-control timer (TIM1) RM0461 Bit 10 BK2CMP1P: BRK2 COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BK2P polarity bit. 0: COMP1 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1) 1: COMP1 input polarity is inverted (active high if BK2P=0, active low if BK2P=1) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 715 RM0461 Advanced-control timer (TIM1) 23.4.29 TIM1 timer input selection register (TIM1_TISEL) Address offset: 0x68 Reset value: 0x0000 0000 Res. Res. Res. Res. TI4SEL[3:0] Res. Res. Res. Res. TI3SEL[3:0] Res. Res. Res. Res. TI2SEL[3:0] Res. Res. Res. Res. TI1SEL[3:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 TI4SEL[3:0]: selects TI4[0] to TI4[15] input 0000: TIM1_CH4 input Others: Reserved...
Page 716: Table 169. Tim1 Register Map And Reset Values
Advanced-control timer (TIM1) RM0461 23.4.30 TIM1 register map TIM1 registers are mapped as 16-bit addressable registers as described in the table below: Table 169. TIM1 register map and reset values Register Offset name TIM1_CR1 [1:0] [1:0] 0x00 Reset value TIM1_CR2 MMS2[3:0] [2:0] 0x04...
Page 717 RM0461 Advanced-control timer (TIM1) Table 169. TIM1 register map and reset values (continued) Register Offset name TIM1_CNT CNT[15:0] 0x24 Reset value TIM1_PSC PSC[15:0] 0x28 Reset value TIM1_ARR ARR[15:0] 0x2C Reset value TIM1_RCR REP[15:0] 0x30 Reset value TIM1_CCR1 CCR1[15:0] 0x34 Reset value TIM1_CCR2 CCR2[15:0] 0x38...
Page 718 Advanced-control timer (TIM1) RM0461 Table 169. TIM1 register map and reset values (continued) Register Offset name TIM1_CCMR3 OC6M OC5M Output [2:0] [2:0] 0x54 Compare mode Reset value TIM1_CCR5 CCR5[15:0] 0x58 Reset value TIM1_CCR6 CCR6[15:0] 0x5C Reset value TIM1_AF1 ETRSEL 0x60 [3:0] Reset value TIM1_AF2...
Page 719 RM0461 General-purpose timer (TIM2) General-purpose timer (TIM2) 24.1 TIM2 introduction The general-purpose timer TIM2 consists of a 32-bit auto-reload counter driven by a programmable prescaler. The timer may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
Page 720: Figure 174. General-Purpose Timer Block Diagram
General-purpose timer (TIM2) RM0461 Figure 174. General-purpose timer block diagram Internal clock (CK_INT) From RCC Trigger ETRF controller TRGO Polarity selection & edge ETRP TIMx_ETR Input filter detector & prescaler to other timers to peripherals ITR[0..15] Slave TRGI Reset, enable, count controller mode TI1F_ED...
Page 721 RM0461 General-purpose timer (TIM2) 24.3 TIM2 functional description 24.3.1 Time-base unit The main block of the programmable timer is a 32-bit counter with its related auto-reload register. The counter can count up, down or both up and down but also down or both up and down.
Page 722: Figure 175. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timer (TIM2) RM0461 Figure 175. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 176.
Page 723: Figure 177. Counter Timing Diagram, Internal Clock Divided By 1
RM0461 General-purpose timer (TIM2) 24.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 724: Figure 178. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timer (TIM2) RM0461 Figure 178. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0035 0036 0000 0001 0002 0003 0034 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V2 Figure 179. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 725: Figure 180. Counter Timing Diagram, Internal Clock Divided By N
RM0461 General-purpose timer (TIM2) Figure 180. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31081V2 Figure 181. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT...
Page 726: Figure 182. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
General-purpose timer (TIM2) RM0461 Figure 182. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timerclock = CK_CNT Counter register F1 F2 F3 F4 F5 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 727: Figure 183. Counter Timing Diagram, Internal Clock Divided By 1
RM0461 General-purpose timer (TIM2) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 183. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 01 00 34 33 32 Counter underflow (cnt_udf) Update event (UEV)
Page 728: Figure 185. Counter Timing Diagram, Internal Clock Divided By 4
General-purpose timer (TIM2) RM0461 Figure 185. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0001 0000 0000 0001 Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31186V1 Figure 186. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register...
Page 729: Figure 187. Counter Timing Diagram, Update Event When Repetition Counter
RM0461 General-purpose timer (TIM2) Figure 187. Counter timing diagram, Update event when repetition counter is not used CK_PSC Timerclock = CK_CNT 30 2F Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31188V1 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the...
Page 730: Figure 188. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
General-purpose timer (TIM2) RM0461 DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 731: Figure 189. Counter Timing Diagram, Internal Clock Divided By 2
RM0461 General-purpose timer (TIM2) Figure 189. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0002 0001 0000 0001 0002 0003 0003 Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31190V1 Figure 190. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 732: Figure 191. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timer (TIM2) RM0461 Figure 191. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31192V1 Figure 192. Counter timing diagram, Update event with ARPE=1 (counter underflow) CK_PSC Timerclock = CK_CNT 05 04 03 02...
Page 733: Figure 193. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow)
RM0461 General-purpose timer (TIM2) Figure 193. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_PSC Timer clock = CK_CNT Counter register 31 30 2F F8 F9 FA FB FC Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active...
Page 734: Figure 194. Control Circuit In Normal Mode, Internal Clock Divided By 1
General-purpose timer (TIM2) RM0461 Figure 194. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 33 34 35 36 03 04 05 MS31085V2 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register.
Page 735: Figure 196. Control Circuit In External Clock Mode 1
RM0461 General-purpose timer (TIM2) Note: The capture prescaler is not used for triggering, so it does not need to be configured. Select rising edge polarity by writing CC2P=0 and CC2NP=0 and CC2NP=0 in the TIMx_CCER register. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.
Page 736: Figure 197. External Trigger Input Block
General-purpose timer (TIM2) RM0461 Figure 197. External trigger input block TI2F TI1F Encoder ETR input or LSE mode TRGI External clock mode 1 CK_PSC ETRP Divider External clock ETRF ETR1..15 inputs from Filter /1, /2, /4, /8 mode 2 on-chip sources downcounter CK_INT Internal clock...
Page 737: Figure 198. Control Circuit In External Clock Mode 2
RM0461 General-purpose timer (TIM2) Figure 198. Control circuit in external clock mode 2 f CK_INT CNT_EN ETRP ETRF Counter clock = CK_CNT =CK_PSC Counter register MSv33111V3 24.3.4 Capture/Compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
Page 738: Figure 200. Capture/Compare Channel 1 Main Circuit
General-purpose timer (TIM2) RM0461 Figure 200. Capture/Compare channel 1 main circuit APB Bus MCU-peripheral interface Input mode Output mode 16/32-bit CC1S[1] Capture/compare preload register CC1S[0] CC1S[1] CC1S[0] Compare IC1PS Capture transfer CC1E OC1PE OC1PE compare shadow register CC1G TIMx_CCMR1 (from time Comparator TIMx_EGR base unit)
Page 739 RM0461 General-purpose timer (TIM2) 24.3.5 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 740: Figure 202. Pwm Input Mode Timing
General-purpose timer (TIM2) RM0461 24.3.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 741 RM0461 General-purpose timer (TIM2) 24.3.7 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (ocxref/OCx) to its active level, one just needs to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register.
Page 742: Figure 203. Output Compare Mode, Toggle On Oc1
General-purpose timer (TIM2) RM0461 The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 203.
Page 743: Figure 204. Edge-Aligned Pwm Waveforms (Arr=8)
RM0461 General-purpose timer (TIM2) cleared by an external event through the ETR signal until the next PWM period), the OCREF signal is asserted only: • When the result of the comparison or • When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from the “frozen”...
Page 744 General-purpose timer (TIM2) RM0461 Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Downcounting mode on page 726. In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then ocxref is held at 100%.
Page 745: Figure 205. Center-Aligned Pwm Waveforms (Arr=8)
RM0461 General-purpose timer (TIM2) Figure 205. Center-aligned PWM waveforms (ARR=8) Counter register OCxREF CCRx = 4 CMS=01 CCxIF CMS=10 CMS=11 OCxREF CCRx=7 CMS=10 or 11 CCxIF ‘1’ OCxREF CCRx=8 CMS=01 CCxIF CMS=10 CMS=11 ‘1’ OCxREF CCRx>8 CMS=01 CCxIF CMS=10 CMS=11 ‘0’...
Page 746: Figure 206. Generation Of 2 Phase-Shifted Pwm Signals With 50% Duty Cycle
General-purpose timer (TIM2) RM0461 24.3.10 Asymmetric PWM mode Asymmetric mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of TIMx_CCRx registers.
Page 747: Figure 207. Combined Pwm Mode On Channels 1 And 3
RM0461 General-purpose timer (TIM2) When a given channel is used as combined PWM channel, its secondary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2). Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones.
Page 748: Figure 208. Clearing Timx Ocxref
General-purpose timer (TIM2) RM0461 The OCxREF signal for a given channel can be reset by applying a high level on the ETRF input (OCxCE enable bit set to 1 in the corresponding TIMx_CCMRx register). OCxREF remains low until the next update event (UEV) occurs. This function can be used only in the output compare and PWM modes.
Page 749: Figure 209. Example Of One-Pulse Mode
RM0461 General-purpose timer (TIM2) 24.3.13 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 750 General-purpose timer (TIM2) RM0461 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 751: Figure 210. Retriggerable One-Pulse Mode
RM0461 General-purpose timer (TIM2) Figure 210. Retriggerable one-pulse mode. TRGI Counter Output MS33106V1 24.3.15 Encoder interface mode To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and TI2 edges.
Page 752: Table 170. Counting Direction Versus Encoder Signals
General-purpose timer (TIM2) RM0461 Table 170. Counting direction versus encoder signals Level on opposite TI1FP1 signal TI2FP2 signal Active edge signal (TI1FP1 for Rising Falling Rising Falling TI2, TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count No Count...
Page 753: Figure 212. Example Of Encoder Interface Mode With Ti1Fp1 Polarity Inverted
RM0461 General-purpose timer (TIM2) Figure 212. Example of encoder interface mode with TI1FP1 polarity inverted forward jitter backward jitter forward Counter down down MS33108V1 The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. Dynamic information can be obtained (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode.
Page 754: Figure 213. Control Circuit In Reset Mode
General-purpose timer (TIM2) RM0461 24.3.18 Timers and external trigger synchronization The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 755: Figure 214. Control Circuit In Gated Mode
RM0461 General-purpose timer (TIM2) Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so it does not need to be configured. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register.
Page 756: Figure 215. Control Circuit In Trigger Mode
General-purpose timer (TIM2) RM0461 CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=00110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
Page 757: Figure 216. Control Circuit In External Clock Mode 2 + Trigger Mode
RM0461 General-purpose timer (TIM2) A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input.
Page 758: Figure 218. Master/Slave Connection Example With 1 Channel Only Timers
General-purpose timer (TIM2) RM0461 Figure 218. Master/slave connection example with 1 channel only timers TIM_mstr TIM_slv Clock Prescaler Counter Output Slave tim_oc1 tim_itr CK_PSC mode control control Compare 1 Prescaler Counter Input TIM_CH1 trigger selection MSv65225V1 Note: The timers with one channel only (see Figure 218) do not feature a master mode.
Page 759: Figure 219. Gating Tim2 With Oc1Ref Of Tim1
RM0461 General-purpose timer (TIM2) Configure TIM1 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register). Configure the TIM1 OC1REF waveform (TIM1_CCMR1 register). Configure TIM2 to get the input trigger from TIM1 (TS=00000 in the TIM2_SMCR register).
Page 760: Figure 220. Gating Tim2 With Enable Of Tim1
General-purpose timer (TIM2) RM0461 Figure 220. Gating TIM2 with Enable of TIM1 CK_INT TIM1-CEN=CNT_EN TIM1-CNT_INIT TIM1-CNT TIM2-CNT TIM2-CNT_INIT TIM2-write CNT TIM2-TIF Write TIF = 0 MS32696V1 Using one timer to start another timer In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to Figure 217 for connections.
Page 761: Figure 222. Triggering Tim2 With Enable Of Tim1
RM0461 General-purpose timer (TIM2) As in the previous example, both counters can be initialized before starting counting. Figure 222 shows the behavior with the same configuration as in Figure 221 but in trigger mode instead of gated mode (SMS=110 in the TIM2_SMCR register). Figure 222.
Page 762 General-purpose timer (TIM2) RM0461 As an example, the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) upon an update event, with the DMA transferring half words into the CCRx registers. This is done in the following steps: Configure the corresponding DMA channel as follows: –...
Page 763 RM0461 General-purpose timer (TIM2) 24.4 TIM2 registers In this section, “TIMx” should be understood as “TIM2” since there is only one instance of this type of timer for the products to which this reference manual applies. Refer to Section 1.2 for a list of abbreviations used in register descriptions.
Page 764 General-purpose timer (TIM2) RM0461 Bit 4 DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source...
Page 765 RM0461 General-purpose timer (TIM2) Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) Section 23.3.25: Interfacing with Hall sensors on page 670 See also Bits 6:4 MMS[2:0]: Master mode selection...
Page 766 General-purpose timer (TIM2) RM0461 24.4.3 TIM2 slave mode control register (TIM2_SMCR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TS[4:3] Res. Res. Res. SMS[3] ETPS[1:0] ETF[3:0] TS[2:0] OCCS SMS[2:0] Bits 31:22 Reserved, must be kept at reset value. Bits 19:17 Reserved, must be kept at reset value.
Page 767 RM0461 General-purpose timer (TIM2) Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 768 General-purpose timer (TIM2) RM0461 Bits 21, 20, 6, 5, 4 TS[4:0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00000: Internal Trigger 0 (ITR0) 00001: Internal Trigger 1 (ITR1) 00010: Internal Trigger 2 (ITR2) 00011: Internal Trigger 3 (ITR3) 00100: TI1 Edge Detector (TI1F_ED) 00101: Filtered Timer Input 1 (TI1FP1)
Page 769: Table 171. Tim2 Internal Trigger Connection
RM0461 General-purpose timer (TIM2) Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 770 General-purpose timer (TIM2) RM0461 Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled. Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled. 1: CC2 DMA request enabled. Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled.
Page 771 RM0461 General-purpose timer (TIM2) Bits 15:13 Reserved, must be kept at reset value. Bit 12 CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description Bit 11 CC3OF: Capture/Compare 3 overcapture flag refer to CC1OF description Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input...
Page 772 General-purpose timer (TIM2) RM0461 Bit 2 CC2IF: Capture/Compare 2 interrupt flag Refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). 0: No compare match / No input capture occurred 1: A compare match or an input capture occurred If channel CC1 is configured as output: this flag is set when the content of the counter...
Page 773 RM0461 General-purpose timer (TIM2) Bit 2 CC2G: Capture/compare 2 generation Refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
Page 774 General-purpose timer (TIM2) RM0461 Bits 9:8 CC2S[1:0]: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1.
Page 775 RM0461 General-purpose timer (TIM2) 24.4.8 TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) Address offset: 0x18 Reset value: 0x0000 0000 The same register can be used for output compare mode (this section) or for input capture mode (previous section). The direction of a channel is defined by configuring the corresponding CCxS bits.
Page 776 General-purpose timer (TIM2) RM0461 Bits 16, 6:4 OC1M[3:0]: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 777 RM0461 General-purpose timer (TIM2) Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 778 General-purpose timer (TIM2) RM0461 Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC.
Page 779 RM0461 General-purpose timer (TIM2) Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC.
Page 780: Table 172. Output Control Bit For Standard Ocx Channels
General-purpose timer (TIM2) RM0461 Bit 7 CC2NP: Capture/Compare 2 output Polarity. Refer to CC1NP description Bit 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable. Refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 output Polarity.
Page 781 RM0461 General-purpose timer (TIM2) Address offset: 0x24 Reset value: 0x0000 0000 CNT[31:16] CNT[15:0] Bits 31:0 CNT[31:0]: counter value 24.4.13 TIM2 counter [alternate] (TIM2_CNT) Bit 31 of this register has two possible definitions depending on the value of UIFREMAP in TIMx_CR1 register: •...
Page 782 General-purpose timer (TIM2) RM0461 24.4.15 TIM2 auto-reload register (TIM2_ARR) Address offset: 0x2C Reset value: 0xFFFF FFFF ARR[31:16] ARR[15:0] Bits 31:0 ARR[31:0]: Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 24.3.1: Time-base unit on page 721 for more details about ARR update and behavior.
Page 783 RM0461 General-purpose timer (TIM2) CCR2[31:16] CCR2[15:0] Bits 31:0 CCR2[31:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE).
Page 784 General-purpose timer (TIM2) RM0461 CCR4[31:16] CCR4[15:0] Bits 31:0 CCR4[31:0]: Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE).
Page 785 RM0461 General-purpose timer (TIM2) 24.4.21 TIM2 DMA address for full transfer (TIM2_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the...
Page 786 General-purpose timer (TIM2) RM0461 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETRSEL[3:2] ETRSEL[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:18 Reserved, must be kept at reset value. Bits 17:14 ETRSEL[3:0]: ETR source selection These bits select the ETR input source.
Page 787: Table 173. Tim2 Register Map And Reset Values
RM0461 General-purpose timer (TIM2) 24.4.25 TIMx register map TIMx registers are mapped as described in the table below: Table 173. TIM2 register map and reset values Register Offset name TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value ETPS TIMx_SMCR ETF[3:0]...
Page 788 General-purpose timer (TIM2) RM0461 Table 173. TIM2 register map and reset values (continued) Register Offset name TIMx_CNT CNT[30:0] 0x24 Reset value TIMx_PSC PSC[15:0] 0x28 Reset value TIMx_ARR ARR[31:0] 0x2C Reset value 0x30 Reserved TIMx_CCR1 CCR1[31:0] 0x34 Reset value TIMx_CCR2 CCR2[31:0] 0x38 Reset value TIMx_CCR3...
Page 789 RM0461 General-purpose timer (TIM2) Table 173. TIM2 register map and reset values (continued) Register Offset name TIM2_TISEL TI2SEL[3:0] TI1SEL[3:0] 0x68 Reset value Refer to Section 2.4 on page 62 for the register boundary addresses. RM0461 Rev 5 789/1306...
Page 790 General-purpose timers (TIM16/TIM17) RM0461 General-purpose timers (TIM16/TIM17) 25.1 TIM16/TIM17 introduction The TIM16/TIM17 timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Page 791: Figure 223. Tim16/Tim17 Block Diagram
RM0461 General-purpose timers (TIM16/TIM17) Figure 223. TIM16/TIM17 block diagram Internal clock (CK_INT) Counter Enable (CEN) REP register To other timers for Auto-reload register cross- Repetition trigerring Stop, clear or up/down counter CK_PSC CK_CNT CNT counter prescaler DTG registers CC1I TI1[0] TIMx_CH1 Input TIMx_CH1...
Page 792 General-purpose timers (TIM16/TIM17) RM0461 25.3 TIM16/TIM17 functional description 25.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 793: Figure 224. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0461 General-purpose timers (TIM16/TIM17) Figure 224. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 225.
Page 794 General-purpose timers (TIM16/TIM17) RM0461 25.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR).
Page 795: Figure 226. Counter Timing Diagram, Internal Clock Divided By 1
RM0461 General-purpose timers (TIM16/TIM17) Figure 226. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 34 35 36 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31078V2 Figure 227. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 796: Figure 228. Counter Timing Diagram, Internal Clock Divided By 4
General-purpose timers (TIM16/TIM17) RM0461 Figure 228. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31080V2 Figure 229. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register...
Page 797: Preloaded)
RM0461 General-purpose timers (TIM16/TIM17) Figure 230. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT 05 06 07 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31082V2 Figure 231.
Page 798 General-purpose timers (TIM16/TIM17) RM0461 25.3.3 Repetition counter Section 25.3.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals. This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N counter overflows, where N is the...
Page 799: Figure 232. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
RM0461 General-purpose timers (TIM16/TIM17) Figure 232. Update rate examples depending on mode and TIMx_RCR register settings Edge-aligned mode Upcounting Counter TIMx_CNT TIMx_RCR = 0 TIMx_RCR = 1 TIMx_RCR = 2 TIMx_RCR = 3 TIMx_RCR = 3 re-synchronization UEV (by SW) Update Event: preload registers transferred to active registers and update interrupt generated.
Page 800: Figure 233. Control Circuit In Normal Mode, Internal Clock Divided By 1
General-purpose timers (TIM16/TIM17) RM0461 Figure 233 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. Figure 233. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN Counter initialization (internal) Counter clock = CK_CNT = CK_PSC Counter register 35 36 03 04 05...
Page 801: Figure 235. Control Circuit In External Clock Mode 1
RM0461 General-purpose timers (TIM16/TIM17) Select the proper TI2[x] source (internal or external) with the TI2SEL[3:0] bits in the TIMx_TISEL register. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000).
Page 802: Figure 236. Capture/Compare Channel (Example: Channel 1 Input Stage)
General-purpose timers (TIM16/TIM17) RM0461 Figure 236. Capture/compare channel (example: channel 1 input stage) TI1F_ED To the slave mode controller TI1[0] TI1F_Rising TI1FP1 Filter Edge TI1[1..15] TI1F_Falling downcounter detector IC1PS TI2FP1 Divider /1, /2, /4, /8 ICF[3:0] CC1P TIMx_CCER TIMx_CCMR1 (from slave mode controller) TI2F_Rising (from channel 2)
Page 803: Figure 238. Output Stage Of Capture/Compare Channel (Channel 1)
RM0461 General-purpose timers (TIM16/TIM17) Figure 238. Output stage of capture/compare channel (channel 1) To the master mode controller Output enable ‘0’ circuit OC1REF OC1REFC OC1_DT CC1P CNT>CCR1 Output Dead-time Output TIM1_CCER mode CNT=CCR1 selector generator controller OC1N_DT Output OC1N ‘0’ OC2REF enable circuit...
Page 804 General-purpose timers (TIM16/TIM17) RM0461 detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in the TIMx_CCER register (rising edge in this case). Program the input prescaler.
Page 805 RM0461 General-purpose timers (TIM16/TIM17) When a match is found between the capture/compare register and the counter, the output compare function: • Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register).
Page 806: Figure 239. Output Compare Mode, Toggle On Oc1
General-purpose timers (TIM16/TIM17) RM0461 Figure 239. Output compare mode, toggle on OC1 Write B201h in the CC1R register B200 B201 TIM1_CNT 0039 003A 003B B201 003A TIM1_CCR1 OC1REF= OC1 Match detected on CCR1 Interrupt generated if enabled MS31092V1 25.3.9 PWM mode Pulse Width Modulation mode allows a signal to be generated with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 807: Figure 240. Edge-Aligned Pwm Waveforms (Arr=8)
RM0461 General-purpose timers (TIM16/TIM17) Figure 240. Edge-aligned PWM waveforms (ARR=8) Counter register OCXREF CCRx=4 CCxIF OCXREF CCRx=8 CCxIF OCXREF ‘1’ CCRx>8 CCxIF ‘0’ OCXREF CCRx=0 CCxIF MS31093V1 25.3.10 Complementary outputs and dead-time insertion The TIM16/TIM17 general-purpose timers can output one complementary signal and manage the switching-off and switching-on of the outputs.
Page 808: Figure 241. Complementary Output With Dead-Time Insertion
General-purpose timers (TIM16/TIM17) RM0461 If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated. The following figures show the relationships between the output signals of the dead-time generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1, CCxE=1 and CCxNE=1 in these examples) Figure 241.
Page 809: Figure 243. Dead-Time Waveforms With Delay Greater Than The Positive Pulse
RM0461 General-purpose timers (TIM16/TIM17) Figure 243. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCxN delay MS31097V1 The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 25.4.14: TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) on page 832 for delay calculation.
Page 810 General-purpose timers (TIM16/TIM17) RM0461 must be inserted (dummy instruction) before reading it correctly. This is because the write acts on the asynchronous signal whereas the read reflects the synchronous signal. When a break occurs (selected level on the break input): •...
Page 811: Figure 244. Output Behavior In Response To A Break
RM0461 General-purpose timers (TIM16/TIM17) Figure 244. Output behavior in response to a break BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay OCxN (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay delay...
Page 812: Table 174. Break Protection Disarming Conditions
General-purpose timers (TIM16/TIM17) RM0461 25.3.12 Bidirectional break inputs The TIM16/TIM17 are featuring bidirectional break I/Os, as represented on Figure 245. They allow the following: • A board-level global break signal available for signaling faults to external MCUs or gate drivers, with a unique pin being both an input and an output status pin •...
Page 813: Figure 245. Output Redirection
RM0461 General-purpose timers (TIM16/TIM17) The following procedure must be followed to re-arm the protection after a break event: • The BKDSRM bit must be set to release the output control • The software must wait until the system break condition disappears (if any) and clear the SBIF status flag (or clear it systematically before re-arming) •...
Page 814: Figure 246. 6-Step Generation, Com Example (Ossr=1)
General-purpose timers (TIM16/TIM17) RM0461 Figure 246. 6-step generation, COM example (OSSR=1) Counter (CNT) tim_ocxref Write COM to 1 COM event CCxE = 1 CCxE = 1 Write OCxM to 0100 CCxNE = 0 CCxNE = 0 OCxM = 0010 (forced inactive) OCxM = 0100 tim_ocx Example 1...
Page 815 RM0461 General-purpose timers (TIM16/TIM17) 25.3.14 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 816: Figure 247. Example Of One Pulse Mode
General-purpose timers (TIM16/TIM17) RM0461 Figure 247. Example of one pulse mode OC1REF TIM1_ARR TIM1_CCR1 DELAY PULSE MS31099V1 For example one may want to generate a positive pulse on OC1 with a length of t PULSE after a delay of t as soon as a positive edge is detected on the TI2 input pin.
Page 817 RM0461 General-purpose timers (TIM16/TIM17) Particular case: OCx fast enable In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay t min we can get.
Page 818 General-purpose timers (TIM16/TIM17) RM0461 For example, the timer DMA burst feature could be used to update the contents of the CCRx registers (x = 2, 3, 4) on an update event, with the DMA transferring half words into the CCRx registers. This is done in the following steps: Configure the corresponding DMA channel as follows: –...
Page 819 RM0461 General-purpose timers (TIM16/TIM17) 25.4 TIM16/TIM17 registers Refer to Section 1.2 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 25.4.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17) Address offset: 0x00 Reset value: 0x0000 UIFRE...
Page 820 General-purpose timers (TIM16/TIM17) RM0461 Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow –...
Page 821 RM0461 General-purpose timers (TIM16/TIM17) Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output.
Page 822 General-purpose timers (TIM16/TIM17) RM0461 25.4.4 TIMx status register (TIMx_SR)(x = 16 to 17) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. CC1OF Res. Res. COMIF Res. Res. Res. CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:10 Reserved, must be kept at reset value. Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode.
Page 823 RM0461 General-purpose timers (TIM16/TIM17) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...
Page 824 General-purpose timers (TIM16/TIM17) RM0461 25.4.6 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 16 to 17) Address offset: 0x18 Reset value: 0x0000 0000 The same register can be used for input capture mode (this section) or for output compare mode (next section).
Page 825 RM0461 General-purpose timers (TIM16/TIM17) Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 826 General-purpose timers (TIM16/TIM17) RM0461 OC1M Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OC1M[2:0] OC1PE OC1FE CC1S[1:0] Bits 31:17 Reserved, must be kept at reset value. Bits 15:7 Reserved, must be kept at reset value.
Page 827 RM0461 General-purpose timers (TIM16/TIM17) Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’...
Page 828 General-purpose timers (TIM16/TIM17) RM0461 Bit 2 CC1NE: Capture/Compare 1 complementary output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
Page 829: Table 175. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
RM0461 General-purpose timers (TIM16/TIM17) Table 175. Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) Control bits Output states MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state Output Disabled (not driven by the timer: Hi-Z) OCx=0 OCxN=0, OCxN_EN=0 Output Disabled (not driven...
Page 830 General-purpose timers (TIM16/TIM17) RM0461 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNT[15:0] Bit 31 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0.
Page 831 RM0461 General-purpose timers (TIM16/TIM17) 25.4.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) Address offset: 0x30 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0] Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e.
Page 832 General-purpose timers (TIM16/TIM17) RM0461 25.4.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) Address offset: 0x44 Reset value: 0x0000 0000 Res. Res. Res. BKBID Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DSRM OSSR OSSI LOCK[1:0] DTG[7:0] Note:...
Page 833 RM0461 General-purpose timers (TIM16/TIM17) Bit 14 AOE: Automatic output enable 0: MOE can be set only by software 1: MOE can be set by software or automatically at the next update event (if the break input is not be active) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 834 General-purpose timers (TIM16/TIM17) RM0461 Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 25.4.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 827).
Page 835 RM0461 General-purpose timers (TIM16/TIM17) Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers.
Page 836 General-purpose timers (TIM16/TIM17) RM0461 25.4.17 TIM16 option register 1 (TIM16_OR1) Address offset: 0x50 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 837 RM0461 General-purpose timers (TIM16/TIM17) Bit 9 BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low 1: BKIN input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 838 General-purpose timers (TIM16/TIM17) RM0461 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1_RMP[1:0] Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 TI1_RMP[1:0]: Timer 17 input 1 connection This bit is set and cleared by software.
Page 839 RM0461 General-purpose timers (TIM16/TIM17) Bit 9 BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low 1: BKIN input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 840: Table 176. Tim16/Tim17 Register Map And Reset Values
General-purpose timers (TIM16/TIM17) RM0461 25.4.23 TIM16/TIM17 register map TIM16/TIM17 registers are mapped as 16-bit addressable registers as described in the table below: Table 176. TIM16/TIM17 register map and reset values Register Offset name TIMx_CR1 [1:0] 0x00 Reset value TIMx_CR2 0x04 Reset value TIMx_DIER 0x0C...
Page 841 RM0461 General-purpose timers (TIM16/TIM17) Table 176. TIM16/TIM17 register map and reset values (continued) Register Offset name TIMx_RCR REP[7:0] 0x30 Reset value TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_BDTR DTG[7:0] 0x44 [1:0] Reset value TIMx_DCR DBL[4:0] DBA[4:0] 0x48 Reset value TIMx_DMAR DMAB[15:0] 0x4C Reset value TI1_...
Page 842 Low-power timer (LPTIM) RM0461 Low-power timer (LPTIM) 26.1 Introduction The LPTIM is a 16-bit timer that benefits from the ultimate developments in power consumption reduction. Thanks to its diversity of clock sources, the LPTIM is able to keep running in all power modes except for Standby mode. Given its capability to run even with no internal clock source, the LPTIM can be used as a “Pulse Counter”...
Page 843: Table 177. Stm32Wlex Lptim Features
26.3 LPTIM implementation Table 177 describes LPTIM implementation on STM32WLEx devices. The full set of features is implemented in LPTIM1. LPTIM2 and LPTIM3 support a smaller set of features, but is otherwise identical to LPTIM1. Table 177. STM32WLEx LPTIM features...
Page 844: Table 178. Lptim Input/Output Pins
Low-power timer (LPTIM) RM0461 26.4.2 LPTIM pins and internal signals The following tables provide the list of LPTIM pins and internal signals, respectively. Table 178. LPTIM input/output pins Names Signal type Description LPTIM_IN1 Digital input LPTIM Input 1 from GPIO pin LPTIM_IN2 Digital input LPTIM Input 2 from GPIO pin...
Page 845: Table 181. Lptim2 External Trigger Connection
RM0461 Low-power timer (LPTIM) Table 181. LPTIM2 external trigger connection TRIGSEL External trigger lptim_ext_trig0 GPIO pin as LPTIM2_ETR alternate function lptim_ext_trig1 RTC ALARM A lptim_ext_trig2 RTC ALARM B lptim_ext_trig3 TAMP1 input detection lptim_ext_trig4 TAMP2 input detection lptim_ext_trig5 TAMP3 input detection lptim_ext_trig6 comp1_out lptim_ext_trig7...
Page 846: Table 185. Lptim2 Input 1 Connection
Low-power timer (LPTIM) RM0461 Table 185. LPTIM2 input 1 connection lptim_in1 LPTIM2 input 1 connected to lptim_in1 GPIO pin as LPTIM2_IN1 alternate function lptim_in1 comp1_out lptim_in1 comp2_out lptim_in1 comp1_out or comp2_out Table 186. LPTIM3 input 1 connection lptim_in1 LPTIM3 input 1 connected to lptim_in1 GPIO pin as LPTIM3_IN1 alternate function lptim_in1...
Page 847: Table 187. Prescaler Division Ratios
RM0461 Low-power timer (LPTIM) The digital filters are divided into two groups: • The first group of digital filters protects the LPTIM internal or external inputs. The digital filters sensitivity is controlled by the CKFLT bits • The second group of digital filters protects the LPTIM internal or external trigger inputs. The digital filters sensitivity is controlled by the TRGFLT bits.
Page 848 Low-power timer (LPTIM) RM0461 26.4.7 Trigger multiplexer The LPTIM counter may be started either by software or after the detection of an active edge on one of the 8 trigger inputs. TRIGEN[1:0] is used to determine the LPTIM trigger source: •...
Page 849: Figure 250. Lptim Output Waveform, Single Counting Mode Configuration When Repetition Register Content Is Different Than Zero (With Preload = 1)
RM0461 Low-power timer (LPTIM) Figure 250. LPTIM output waveform, single counting mode configuration when repetition register content is different than zero (with PRELOAD = 1) LPTIM_RCR Repetition counter LPTIM_ARR Compare External trigger event Ignored external trigger event MSv47414V1 - Set-once mode activated: It should be noted that when the WAVE bitfield in the LPTIM_CFGR register is set, the Set- once mode is activated.
Page 850: Figure 252. Lptim Output Waveform, Continuous Counting Mode Configuration
Low-power timer (LPTIM) RM0461 Figure 252. LPTIM output waveform, Continuous counting mode configuration Discarded triggers LPTIM_ARR Compare External trigger event MSv39229V2 SNGSTRT and CNTSTRT bits can only be set when the timer is enabled (The ENABLE bit is set to ‘1’). It is possible to change “on the fly” from One-shot mode to Continuous mode. If the Continuous mode was previously selected, setting SNGSTRT switches the LPTIM to the One-shot mode.
Page 851: Figure 253. Waveform Generation
RM0461 Low-power timer (LPTIM) The LPTIM output waveform can be configured through the WAVE bit as follow: • Resetting the WAVE bit to ‘0’ forces the LPTIM to generate either a PWM waveform or a One pulse waveform depending on which bit is set: CNTSTRT or SNGSTRT. •...
Page 852 Low-power timer (LPTIM) RM0461 The LPTIM APB interface and the LPTIM kernel logic use different clocks, so there is some latency between the APB write and the moment when these values are available to the counter comparator. Within this latency period, any additional write into these registers must be avoided.
Page 853 RM0461 Low-power timer (LPTIM) 26.4.13 Timer enable The ENABLE bit located in the LPTIM_CR register is used to enable/disable the LPTIM kernel logic. After setting the ENABLE bit, a delay of two counter clock is needed before the LPTIM is actually enabled. The LPTIM_CFGR and LPTIM_IER registers must be modified only when the LPTIM is disabled.
Page 854: Table 188. Encoder Counting Scenarios
Low-power timer (LPTIM) RM0461 26.4.15 Encoder mode This mode allows handling signals from quadrature encoders used to detect angular position of rotary elements. Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value programmed into the LPTIM_ARR register (0 up to ARR or ARR down to 0 depending on the direction).
Page 855: Figure 254. Encoder Mode Counting Sequence
RM0461 Low-power timer (LPTIM) Figure 254. Encoder mode counting sequence Counter down MS32491V1 26.4.16 Repetition Counter The LPTIM features a repetition counter that decrements by 1 each time an LPTIM counter overflow event occurs. A repetition counter underflow event is generated when the repetition counter contains zero and the LPTIM counter overflows.
Page 856: Different From Zero (With Preload = 1)
Low-power timer (LPTIM) RM0461 Figure 255. Continuous counting mode when repetition register LPTIM_RCR different from zero (with PRELOAD = 1) Repetition counter underflow event LPTIM_RCR Repetition counter LPTIM_ARR Preloaded registers updated Compare MSv47415V1 A repetition counter underflow event is systematically associated with LPTIM preloaded registers update (refer to section "Register update"...
Page 857: Table 189. Effect Of Low-Power Modes On The Lptim
RM0461 Low-power timer (LPTIM) 26.5 LPTIM low-power modes Table 189. Effect of low-power modes on the LPTIM Mode Description Sleep No effect. LPTIM interrupts cause the device to exit Sleep mode. If the LPTIM is clocked by an oscillator available in Stop mode, LPTIM is functional Stop and the interrupts cause the device to exit the Stop mode (refer to Section 26.3: LPTIM...
Page 858 Low-power timer (LPTIM) RM0461 Table 190. Interrupt events (continued) Interrupt event Description Interrupt flag is raised when the repetition counter underflows (or contains Update Event zero) and the LPTIM counter overflows. Repetition register REPOK is set by hardware to inform application that the APB bus write update Ok operation to the LPTIM_RCR register has been successfully completed.
Page 859 RM0461 Low-power timer (LPTIM) Bit 3 CMPOK: Compare register update OK CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed. Bit 2 EXTTRIG: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred.
Page 860 Low-power timer (LPTIM) RM0461 Bit 2 EXTTRIGCF: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register Bit 1 ARRMCF: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register Bit 0 CMPMCF: Compare match clear flag Writing 1 to this bit clears the CMP flag in the LPTIM_ISR register 26.7.3...
Page 861 RM0461 Low-power timer (LPTIM) Bit 2 EXTTRIGIE: External trigger valid edge Interrupt Enable EXTTRIG interrupt disabled EXTTRIG interrupt enabled Bit 1 ARRMIE: Autoreload match Interrupt Enable ARRM interrupt disabled ARRM interrupt enabled Bit 0 CMPMIE: Compare match Interrupt Enable CMPM interrupt disabled CMPM interrupt enabled Caution: The LPTIM_IER register must only be modified when the LPTIM is disabled (ENABLE bit reset to ‘0’) 26.7.4...
Page 862 Low-power timer (LPTIM) RM0461 Bit 21 WAVPOL: Waveform shape polarity The WAVPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers Bit 20 WAVE: Waveform shape The WAVE bit controls the output shape...
Page 863 RM0461 Low-power timer (LPTIM) Bits 7:6 TRGFLT[1:0]: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as...
Page 864 Low-power timer (LPTIM) RM0461 26.7.5 LPTIM control register (LPTIM_CR) Address offset: 0x010 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. COUN Res. Res. Res. Res. Res. Res. Res. Res.
Page 865 RM0461 Low-power timer (LPTIM) 26.7.6 LPTIM compare register (LPTIM_CMP) Address offset: 0x014 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CMP[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CMP[15:0]: Compare value CMP is the compare value used by the LPTIM.
Page 866 Low-power timer (LPTIM) RM0461 26.7.8 LPTIM counter register (LPTIM_CNT) Address offset: 0x01C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNT[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CNT[15:0]: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values.
Page 867 RM0461 Low-power timer (LPTIM) 26.7.10 LPTIM2 option register (LPTIM2_OR) Address offset: 0x020 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 868 Low-power timer (LPTIM) RM0461 26.7.12 LPTIM repetition register (LPTIM_RCR) Address offset: 0x028 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0] Bits 31:8 Reserved, must be kept at reset value.
Page 869: Table 191. Lptim Register Map And Reset Values
RM0461 Low-power timer (LPTIM) 26.7.13 LPTIM register map The following table summarizes the LPTIM registers. Table 191. LPTIM register map and reset values Offset Register name LPTIM_ISR 0x000 0 0 0 0 0 0 0 0 0 Reset value LPTIM_ICR 0x004 0 0 0 0 0 0 0 0 0 Reset value...
Page 870 Low-power timer (LPTIM) RM0461 Table 191. LPTIM register map and reset values (continued) Offset Register name LPTIM3_OR 0x020 Reset value REP[7:0] LPTIM_RCR 0x028 0 0 0 0 0 0 0 0 Reset value 1. If LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section 26.3: LPTIM implementation.
Page 871: Figure 256. Irtim Internal Hardware Connections With Tim16 And Tim17
RM0461 Infrared interface (IRTIM) Infrared interface (IRTIM) An infrared interface (IRTIM) for remote control is available on the device. It can be used with an infrared LED to perform remote control functions. It uses internal connections withTIM16 and TIM17 as shown in Figure 256.
Page 872: Figure 257. Independent Watchdog Block Diagram
Independent watchdog (IWDG) RM0461 Independent watchdog (IWDG) 28.1 Introduction The devices feature an embedded watchdog peripheral that offers a combination of high safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral detects and solves malfunctions due to software failure, and triggers system reset when the counter reaches a given timeout value.
Page 873 RM0461 Independent watchdog (IWDG) When the independent watchdog is started by writing the value 0x0000 CCCC in the IWDG key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). Whenever the key value 0x0000 AAAA is written in the IWDG key register (IWDG_KR), the...
Page 874 Independent watchdog (IWDG) RM0461 28.3.3 Hardware watchdog If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the IWDG key register (IWDG_KR) is written by the software before the counter reaches end of count or if the downcounter is reloaded inside the window.
Page 875 RM0461 Independent watchdog (IWDG) 28.4 IWDG registers Refer to Section 1.2 on page 55 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 28.4.1 IWDG key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) Res.
Page 876 Independent watchdog (IWDG) RM0461 28.4.2 IWDG prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 877 RM0461 Independent watchdog (IWDG) 28.4.3 IWDG reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RL[11:0] Bits 31:12 Reserved, must be kept at reset value.
Page 878 Independent watchdog (IWDG) RM0461 28.4.4 IWDG status register (IWDG_SR) Address offset: 0x0C Reset value: 0x0000 0000 (not reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 879 RM0461 Independent watchdog (IWDG) 28.4.5 IWDG window register (IWDG_WINR) Address offset: 0x10 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WIN[11:0] Bits 31:12 Reserved, must be kept at reset value.
Page 880: Table 192. Iwdg Register Map And Reset Values
Independent watchdog (IWDG) RM0461 28.4.6 IWDG register map The following table gives the IWDG register map and reset values. Table 192. IWDG register map and reset values Register Offset name IWDG_KR KEY[15:0] 0x00 Reset value IWDG_PR PR[2:0] 0x04 Reset value IWDG_RLR RL[11:0] 0x08...
Page 881 RM0461 System window watchdog (WWDG) System window watchdog (WWDG) 29.1 Introduction The system window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the down-counter before the T6 bit becomes cleared.
Page 882: Table 193. Wwdg Internal Input/Output Signals
System window watchdog (WWDG) RM0461 29.3.1 WWDG block diagram Figure 258. Watchdog block diagram WWDG Register interface CMP = 1 when T[6:0] > W[6:0] W[6:0] WWDG_CFR wwdg_out_rst WWDG_SR WDGA Write to WWDG_CR T[6:0] readback WWDG_CR T[6:0] wwdg_it EWIF cnt_out preload 7-bit DownCounter (CNT) WDGTB pclk...
Page 883: Figure 259. Window Watchdog Timing Diagram
RM0461 System window watchdog (WWDG) Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 29.3.5 How to program the watchdog timeout Use the formula in Figure 259 to calculate the WWDG timeout.
Page 884 System window watchdog (WWDG) RM0461 As an example, if APB frequency is 48 MHz, WDGTB[2:0] is set to 3 and T[5:0] is set to 63: ⁄ × × × t WWDG 48000 4096 43.69ms Refer to the datasheet for the minimum and maximum values of t WWDG 29.3.6 Debug mode...
Page 885 RM0461 System window watchdog (WWDG) Bits 31:8 Reserved, must be kept at reset value. Bit 7 WDGA: Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
Page 886: Table 194. Wwdg Register Map And Reset Values
System window watchdog (WWDG) RM0461 29.5.3 WWDG status register (WWDG_SR) Address offset: 0x008 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 887 RM0461 Real-time clock (RTC) Real-time clock (RTC) 30.1 Introduction The RTC provides an automatic wakeup to manage all low-power modes. The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time- of-day clock/calendar with programmable alarm interrupts. As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low-power mode or under reset).
Page 888 Real-time clock (RTC) RM0461 30.3 RTC functional description 30.3.1 RTC block diagram Figure 260. RTC block diagram rtc_tamp_evt rtc_its Time stamp detection RTC_TS Time stamp registers RTC_TSTR RTC_TSDR RTC_TSSR RTC_REFIN ck_spre RTC_PRER RTC_CALR RTC_PRER (default 1 Hz) rtc_ker_ck Asynchronous Smooth Synchronous rtc_calovf prescaler...
Page 889: Table 195. Rtc Input/Output Pins
RM0461 Real-time clock (RTC) 30.3.2 RTC pins and internal signals Table 195. RTC input/output pins Pin name Signal type Description RTC_TS Input RTC timestamp input RTC_REFIN Input RTC 50 or 60 Hz reference clock input RTC_OUT1 Output RTC output 1 RTC_OUT2 Output RTC output 2...
Page 890: Table 197. Rtc Interconnection
Real-time clock (RTC) RM0461 Table 197. RTC interconnection Signal name Source/destination rtc_its From power controller (PWR): main power loss/switch to V detection output rtc_tamp_evt From TAMP peripheral: tamp_evt rtc_calovf To TAMP peripheral: tamp_itamp5 The triggers outputs can be used as triggers for other peripherals. 30.3.3 GPIOs controlled by the RTC and TAMP The GPIOs included in the Battery Backup Domain (V...
Page 891 RM0461 Real-time clock (RTC) Table 198. PC13 configuration (continued) PC13 Pin function 01 or 10 or Don’t Don’t Don’t Don’t No pull care care care care 01 or 10 or TAMPALRM output 01 or Open-Drain 10 or Internal Don’t Don’t Don’t Don’t pull-up...
Page 892: Table 199. Rtc_Out Mapping
Real-time clock (RTC) RM0461 Table 198. PC13 configuration (continued) PC13 Pin function Don’t care Wakeup pin or Standard Don’t Don’t GPIO care care Don’t Don’t care care 1. OD: open drain; PP: push-pull. 2. In this configuration the GPIO must be configured in input. In addition, it is possible to output RTC_OUT2 on PA4 pin thanks to OUT2EN bit.
Page 893 RM0461 Real-time clock (RTC) BCD mode (BIN=00) A programmable prescaler stage generates a 1 Hz clock which is used to update the calendar. To minimize power consumption, the prescaler is split into 2 programmable prescalers (see Figure 260: RTC block diagram): •...
Page 894 Real-time clock (RTC) RM0461 used to define when the calendar is incremented by 1 second, using the SSR least significant bits. 30.3.5 Real-time clock and calendar The RTC calendar time and date registers are accessed through shadow registers which are synchronized with PCLK (APB clock). They can also be accessed directly in order to avoid waiting for the synchronization duration.
Page 895 RM0461 Real-time clock (RTC) When the binary mode is used, the subsecond field can be programmed in the alarm binary register RTC_ALRMABINR. The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR register. Caution: If the seconds field is selected (MSK1 bit reset in RTC_ALRMAR), the synchronous prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct behavior.
Page 896 Real-time clock (RTC) RM0461 30.3.9 RTC initialization and configuration RTC Binary, BCD or Mixed mode By default the RTC is in BCD mode (BIN = 00 in the RTC_ICSR register): the RTC_SSR register contains the sub-second field SS[15:0], clocked by ck_apre, allowing the generation of a 1 Hz clock to update the calendar registers in BCD format (RTC_TR and RTC_DR).
Page 897 RM0461 Real-time clock (RTC) If LPCAL=0: INITF is set around 2 RTCCLK cycles after INIT bit is set. If LPCAL=1: INITF is set up to 2 ck_apre cycle after INIT bit is set. To generate a 1 Hz clock for the calendar counter, program both the prescaler factors in RTC_PRER register, plus BIN and BCDU in the RTC_ICSR register.
Page 898 Real-time clock (RTC) RM0461 Note: Each change of the RTC_CR register is taken into account after around 2 RTCCLK clock cycles due to clock synchronization. Programming the wakeup timer The following sequence is required to configure or change the wakeup timer auto-reload value (WUT[15:0] in RTC_WUTR): Clear WUTE in RTC_CR to disable the wakeup timer.
Page 899 RM0461 Real-time clock (RTC) After an initialization (refer to Calendar initialization and configuration on page 896): the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. After synchronization (refer to Section 30.3.12: RTC synchronization): the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers.
Page 900 Real-time clock (RTC) RM0461 The shift operation consists in adding the SUBFS[14:0] value to the synchronous prescaler counter SS[15:0]: this delays the clock. If at the same time the ADD1S bit is set in BCD or mixed mode, this results in adding one second and at the same time subtracting a fraction of second, so this advances the clock.
Page 901 RM0461 Real-time clock (RTC) When the RTC_REFIN detection is enabled, PREDIV_A and PREDIV_S must be set to their default values: • PREDIV_A = 0x007F • PREVID_S = 0x00FF Note: RTC_REFIN clock detection is not available in Standby mode. 30.3.14 RTC smooth digital calibration The RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a range from -487.1 ppm to +488.5 ppm.
Page 902 Real-time clock (RTC) RM0461 The formula to calculate the effective calibrated frequency (F ) given the input frequency ) is as follows: RTCCLK x [1 + (CALP x 512 - CALM) / (2 + CALM - CALP x 512)] RTCCLK Caution: PREDIV_A must be greater or equal to 3.
Page 903 RM0461 Real-time clock (RTC) In this case, the RTC precision can be measured during 16 seconds with a maximum error of 0.954 ppm (0.5 RTCCLK cycles over 16 seconds). However, since the calibration resolution is reduced, the long term RTC precision is also reduced to 0.954 ppm: CALM[0] bit is stuck at 0 when CALW16 is set to 1.
Page 904 Real-time clock (RTC) RM0461 Caution: If a timestamp event occurs immediately after the TSF bit is supposed to be cleared, then both TSF and TSOVF bits are set. To avoid masking a timestamp event occurring at the same moment, the application must not write 0 into TSF bit unless it has already read it to 1. Optionally, a tamper event can cause a timestamp to be recorded.
Page 905: Table 200. Effect Of Low-Power Modes On Rtc
RM0461 Real-time clock (RTC) 30.4 RTC low-power modes Table 200. Effect of low-power modes on RTC Mode Description No effect Sleep RTC interrupts cause the device to exit the Sleep mode. The RTC remains active when the RTC clock source is LSE or LSI. RTC interrupts Stop cause the device to exit the Stop mode.
Page 906: Table 202. Interrupt Requests
Real-time clock (RTC) RM0461 30.5 RTC interrupts The interrupt channel is set in the masked interrupt status register. The interrupt output is also activated. Table 202. Interrupt requests Exit from Interrupt Exit from Exit from Interrupt Event Enable Stop and Interrupt event clear Sleep...
Page 907 RM0461 Real-time clock (RTC) 30.6 RTC registers Refer to Section 1.2 on page 55 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 30.6.1 RTC time register (RTC_TR) The RTC_TR is the calendar time shadow register.
Page 908 Real-time clock (RTC) RM0461 30.6.2 RTC date register (RTC_DR) The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page 896 Reading the calendar on page 898.
Page 909 RM0461 Real-time clock (RTC) 30.6.3 RTC sub second register (RTC_SSR) Address offset: 0x08 Backup domain reset value: 0x0000 0000 System reset value: 0x0000 0000 (when BYPSHAD = 0, not affected when BYPSHAD = 1) SS[31:16] SS[15:0] Bits 31:0 SS[31:0]: Synchronous binary counter SS[31:16]: Synchronous binary counter MSB values When Binary or Mixed mode is selected (BIN = 01 or 10 or 11): SS[31:16] are the 16 MSB of the SS[31:0] free-running down-counter.
Page 910 Real-time clock (RTC) RM0461 Bits 31:17 Reserved, must be kept at reset value. Bit 16 RECALPF: Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0.
Page 911 RM0461 Real-time clock (RTC) Bit 3 SHPF: Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed.
Page 912 Real-time clock (RTC) RM0461 30.6.6 RTC wakeup timer register (RTC_WUTR) This register can be written only when WUTWF is set to 1 in RTC_ICSR. Address offset: 0x14 Backup domain reset value: 0x0000 FFFF System reset: not affected WUTOCLR[15:0] WUT[15:0] Bits 31:16 WUTOCLR[15:0]: Wakeup auto-reload output clear value When WUTOCLR[15:0] is different from 0x0000, WUTF is set by hardware when the auto- reload down-counter reaches 0 and is cleared by hardware when the auto-reload downcounter reaches WUTOCLR[15:0].
Page 913 RM0461 Real-time clock (RTC) Bit 31 OUT2EN: RTC_OUT2 output enable Setting this bit allows the RTC outputs to be remapped on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL ≠ 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL ≠...
Page 914 Real-time clock (RTC) RM0461 Bit 19 COSEL: Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. 0: Calibration output is 512 Hz 1: Calibration output is 1 Hz These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255).
Page 915 RM0461 Real-time clock (RTC) Bit 7 SSRUIE: SSR underflow interrupt enable 0: SSR underflow interrupt disabled 1: SSR underflow interrupt enabled Bit 6 FMT: Hour format 0: 24 hour/day format 1: AM/PM hour format Bit 5 BYPSHAD: Bypass the shadow registers 0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles.
Page 916 Real-time clock (RTC) RM0461 30.6.8 RTC write protection register (RTC_WPR) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 917 RM0461 Real-time clock (RTC) Bits 31:16 Reserved, must be kept at reset value. Bit 15 CALP: Increase frequency of RTC by 488.5 ppm 0: No RTCCLK pulses are added. 1: One RTCCLK pulse is effectively inserted every 2 pulses (frequency increased by 488.5 ppm).
Page 918 Real-time clock (RTC) RM0461 Bit 31 ADD1S: Add one second 0: No effect 1: Add one second to the clock/calendar This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR).
Page 919 RM0461 Real-time clock (RTC) Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. 30.6.12 RTC timestamp date register (RTC_TSDR) The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset.
Page 920 Real-time clock (RTC) RM0461 Bits 31:0 SS[31:0]: Sub second value/Synchronous binary counter values SS[31:0] is the value of the synchronous prescaler counter when the timestamp event occurred. 30.6.14 RTC alarm A register (RTC_ALRMAR) This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.
Page 921 RM0461 Real-time clock (RTC) Bit 7 MSK1: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds don’t care in alarm A comparison Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. 30.6.15 RTC alarm A sub second register (RTC_ALRMASSR) This register can be written only when ALRAE is reset in RTC_CR register, or in initialization...
Page 922 Real-time clock (RTC) RM0461 30.6.16 RTC alarm B register (RTC_ALRMBR) This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. Address offset: 0x48 Backup domain reset value: 0x0000 0000 System reset: not affected MSK4 DT[1:0] DU[3:0]...
Page 923 RM0461 Real-time clock (RTC) 30.6.17 RTC alarm B sub second register (RTC_ALRMBSSR) This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. Address offset: 0x4C Backup domain reset value: 0x0000 0000 System reset: not affected SSCLR Res.
Page 924 Real-time clock (RTC) RM0461 30.6.18 RTC status register (RTC_SR) Address offset: 0x50 Backup domain reset value: 0x0000 0000 System reset: not affected Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 925 RM0461 Real-time clock (RTC) 30.6.19 RTC masked interrupt status register (RTC_MISR) Address offset: 0x54 Backup domain reset value: 0x0000 0000 System reset: not affected Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSOV ALRB ALRA...
Page 926 Real-time clock (RTC) RM0461 30.6.20 RTC status clear register (RTC_SCR) Address offset: 0x5C Backup domain reset value: 0x0000 0000 System reset: not affected Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CSSR CITS CTSOV CWUT...
Page 927 RM0461 Real-time clock (RTC) 30.6.21 RTC alarm A binary mode register (RTC_ALRABINR) This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode. Address offset: 0x70 Backup domain reset value: 0x0000 0000 System reset: not affected SS[31:16] SS[15:0] Bits 31:0 SS[31:0]: Synchronous counter alarm value in Binary mode...
Page 928: Table 203. Rtc Register Map And Reset Values
Real-time clock (RTC) RM0461 30.6.23 RTC register map Table 203. RTC register map and reset values Offset Register RTC_TR HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] 0x00 Reset value RTC_DR YT[3:0] YU[3:0] WDU[2:0] MU[3:0] DU[3:0] [1:0] 0x04 Reset value RTC_SSR SS[31:16] SS[15:0] 0x08 Reset value...
Page 929 RM0461 Real-time clock (RTC) Table 203. RTC register map and reset values (continued) Offset Register RTC_ALRMAR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] [1:0] 0x40 Reset value RTC_ MASKSS SS[14:0] ALRMASSR [5:0] 0x44 Reset value RTC_ALRMBR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0]...
Page 930 Tamper and backup registers (TAMP) RM0461 Tamper and backup registers (TAMP) 31.1 Introduction 20 32-bit backup registers are retained in all low-power modes and also in V mode. They can be used to store sensitive data as their content is protected by an tamper detection circuit.
Page 931: Figure 261. Tamp Block Diagram
RM0461 Tamper and backup registers (TAMP) 31.3 TAMP functional description 31.3.1 TAMP block diagram Figure 261. TAMP block diagram tamp_ker_ck clock domain Internal tamper detection tamp_itamp1 ITAMP1F ITAMP1 tamp_itampy ITAMPyF ITAMPy Monotonic ITAMP8F counter ITAMP8 overflow TAMP1F Tamper detection TAMP_IN1 EDGE detection tamp_trg1 LEVEL detection...
Page 932: Table 204. Tamp Input/Output Pins
Tamper and backup registers (TAMP) RM0461 31.3.2 TAMP pins and internal signals Table 204. TAMP input/output pins Pin name Signal type Description TAMP_INx (x = pin index) Input Tamper input pin Table 205. TAMP internal input/output signals Internal signal name Signal type Description TAMP kernel clock, connected to rtc_ker_ck...
Page 933 RM0461 Tamper and backup registers (TAMP) 31.3.3 TAMP register write protection After system reset, the TAMP registers (including backup registers) are protected against parasitic write access by the DBP bit in the power control peripheral (refer to the PWR power control section). DBP bit must be set in order to enable TAMP registers write access. 31.3.4 Tamper detection The tamper detection can be configured for the following purposes:...
Page 934 Tamper and backup registers (TAMP) RM0461 Trigger output generation on tamper event The tamper event detection can be used as trigger input by the low-power timers. When TAMPxMSK bit in cleared in TAMP_CR register, the TAMPxF flag must be cleared by software in order to allow a new tamper detection on the same pin.
Page 935: Table 207. Effect Of Low-Power Modes On Tamp
RM0461 Tamper and backup registers (TAMP) The trade-off between tamper detection latency and power consumption through the pull-up can be optimized by using TAMPFREQ to determine the frequency of the sampling for level detection. Note: Refer to the microcontroller datasheet for the electrical characteristics of the pull-up resistors.
Page 936 Tamper and backup registers (TAMP) RM0461 31.6 TAMP registers Refer to Section 1.2 on page 55 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 31.6.1 TAMP control register 1 (TAMP_CR1) Address offset: 0x00 Backup domain reset value: 0xFFFF 0000 System reset: not affected...
Page 937 RM0461 Tamper and backup registers (TAMP) Bit 2 TAMP3E: Tamper detection on TAMP_IN3 enable 0: Tamper detection on TAMP_IN3 is disabled. 1: Tamper detection on TAMP_IN3 is enabled. Bit 1 TAMP2E: Tamper detection on TAMP_IN2 enable 0: Tamper detection on TAMP_IN2 is disabled. 1: Tamper detection on TAMP_IN2 is enabled.
Page 938 Tamper and backup registers (TAMP) RM0461 Bit 23 BKERASE: Backup registers erase Writing ‘1’ to this bit reset the backup registers . Writing 0 has no effect. This bit is always read as 0. Bits 22:19 Reserved, must be kept at reset value. Bit 18 TAMP3MSK: Tamper 3 mask 0: Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection.
Page 939 RM0461 Tamper and backup registers (TAMP) Bits 31:8 Reserved, must be kept at reset value. Bit 7 ITAMP8NOER: Internal Tamper 8 no erase 0: Internal Tamper 8 event erases the backup registers. 1: Internal Tamper 8 event does not erase the backup registers Bit 6 Reserved, must be kept at reset value.
Page 940 Tamper and backup registers (TAMP) RM0461 Bits 6:5 TAMPPRCH[1:0]: TAMP_INx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs. 0x0: 1 RTCCLK cycle 0x1: 2 RTCCLK cycles 0x2: 4 RTCCLK cycles 0x3: 8 RTCCLK cycles...
Page 941 RM0461 Tamper and backup registers (TAMP) Bit 21 ITAMP6IE: Internal tamper 6 interrupt enable 0: Internal tamper 6 interrupt disabled. 1: Internal tamper 6 interrupt enabled. Bit 20 ITAMP5IE: Internal tamper 5 interrupt enable 0: Internal tamper 5 interrupt disabled. 1: Internal tamper 5 interrupt enabled.
Page 942 Tamper and backup registers (TAMP) RM0461 Bit 21 ITAMP6F: Internal tamper 6 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 6. Bit 20 ITAMP5F: Internal tamper 5 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 5.
Page 943 RM0461 Tamper and backup registers (TAMP) Bit 18 ITAMP3MF: Internal tamper 3 interrupt masked flag This flag is set by hardware when the internal tamper 3 interrupt is raised. Bit 17 Reserved, must be kept at reset value. Bit 16 Reserved, must be kept at reset value. Bits 15:3 Reserved, must be kept at reset value.
Page 944 Tamper and backup registers (TAMP) RM0461 Bit 2 CTAMP3F: Clear TAMP3 detection flag Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register. Bit 1 CTAMP2F: Clear TAMP2 detection flag Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register. Bit 0 CTAMP1F: Clear TAMP1 detection flag Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register.
Page 945 RM0461 Tamper and backup registers (TAMP) 31.6.9 TAMP monotonic counter register (TAMP_COUNTR) Address offset: 0x040 Backup domain reset value: 0x0000 0000 System reset: not affected COUNT[31:16] COUNT[15:0] Bits 31:0 COUNT[31:0]: This register is read-only only and is incremented by one when a write access is done to this register.
Page 946: Table 209. Tamp Register Map And Reset Values
Tamper and backup registers (TAMP) RM0461 31.6.11 TAMP register map Table 209. TAMP register map and reset values Offset Register TAMP_CR1 0x00 Reset value TAMP_CR2 0x04 Reset value TAMP_CR3 0x08 Reset value TAMP_FLTCR 0x0C Reset value TAMP_IER 0x2C Reset value TAMP_SR 0x30 Reset value...
Page 947 RM0461 Inter-integrated circuit (I2C) interface Inter-integrated circuit (I2C) interface 32.1 Introduction The I C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial I C bus. It provides multimaster capability, and controls all I bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
Page 948: Table 210. Stm32Wlex I2C Implementation
Wakeup from Stop mode on address match. 32.3 I2C implementation The devices incorporate up to three I²C-bus controllers, I2C1, I2C2, and I2C3, with full or limited feature sets as shown in the following table. Table 210. STM32WLEx I2C implementation I2C features I2C1 I2C2 I2C3...
Page 949: Figure 262. I2C Block Diagram
RM0461 Inter-integrated circuit (I2C) interface 32.4.1 I2C block diagram The block diagram of the I2C interface is shown in Figure 262. Figure 262. I2C block diagram I2CCLK i2c_ker_ck Data control Digital Analog Shift register noise noise GPIO I2C_SDA filter filter logic SMBUS generation/...
Page 950: Table 211. I2C Input/Output Pins
Inter-integrated circuit (I2C) interface RM0461 32.4.2 I2C pins and internal signals Table 211. I2C input/output pins Pin name Signal type Description I2C_SDA Bidirectional I2C data I2C_SCL Bidirectional I2C clock I2C_SMBA Bidirectional SMBus alert Table 212. I2C internal input/output signals Internal signal name Signal type Description i2c_ker_ck...
Page 951: Figure 263. I2C Bus Protocol
RM0461 Inter-integrated circuit (I2C) interface By default, it operates in slave mode. The interface automatically switches from slave to master when it generates a START condition, and from master to slave if an arbitration loss or a STOP generation occurs, allowing multimaster capability. Communication flow In Master mode, the I2C interface initiates a data transfer and generates the clock signal.
Page 952: Table 213. Comparison Of Analog Vs. Digital Filters
Inter-integrated circuit (I2C) interface RM0461 user can disable this analog filter by setting the ANFOFF bit, and/or select a digital filter by configuring the DNF[3:0] bit in the I2C_CR1 register. When the digital filter is enabled, the level of the SCL or the SDA line is internally changed only if it remains stable for more than DNF x I2CCLK periods.
Page 953: Figure 264. Setup And Hold Timings
RM0461 Inter-integrated circuit (I2C) interface I2C timings The timings must be configured in order to guarantee correct data hold and setup times, used in master and slave modes. This is done by programming the PRESC[3:0], SCLDEL[3:0] and SDADEL[3:0] bits in the I2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C configuration window.
Page 954 Inter-integrated circuit (I2C) interface RM0461 • When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is where = SDADEL x t = (PRESC+1) SDADEL PRESC I2CCLK PRESC I2CCLK impacts the hold time SDADEL HD;DAT.
Page 955: Table 214. I2C-Smbus Specification Data Setup And Hold Times
RM0461 Inter-integrated circuit (I2C) interface transmission and reception modes. In transmission mode, if the data is not yet written in I2C_TXDR when SDADEL counter is finished, the I2C keeps on stretching SCL low until the next data is written. Then new data MSB is sent on SDA output, and SCLDEL counter starts, continuing stretching SCL low to guarantee the data setup time.
Page 956: Figure 265. I2C Initialization Flow
Inter-integrated circuit (I2C) interface RM0461 Figure 265. I2C initialization flow Initial settings Clear PE bit in I2C_CR1 Configure ANFOFF and DNF[3:0] in I2C_CR1 Configure PRESC[3:0], SDADEL[3:0], SCLDEL[3:0], SCLH[7:0], SCLL[7:0] in I2C_TIMINGR Configure NOSTRETCH in I2C_CR1 Set PE bit in I2C_CR1 MS19847V2 32.4.6 Software reset...
Page 957: Figure 266. Data Reception
RM0461 Inter-integrated circuit (I2C) interface 32.4.7 Data transfer The data transfer is managed through transmit and receive data registers and a shift register. Reception The SDA input fills the shift register. After the eighth SCL pulse (when the complete data byte is received), the shift register is copied into I2C_RXDR register if it is empty (RXNE = 0).
Page 958: Figure 267. Data Transmission
Inter-integrated circuit (I2C) interface RM0461 Transmission If the I2C_TXDR register is not empty (TXE=0), its content is copied into the shift register after the ninth SCL pulse (the Acknowledge pulse). Then the shift register content is shifted out on SDA line. If TXE = 1, meaning that no data is written yet in I2C_TXDR, SCL line is stretched low until I2C_TXDR is written.
Page 959: Table 215. I2C Configuration
RM0461 Inter-integrated circuit (I2C) interface When RELOAD=0 in master mode, the counter can be used in two modes: • Automatic end mode (AUTOEND = ‘1’ in the I2C_CR2 register). In this mode, the master automatically sends a STOP condition once the number of bytes programmed in the NBYTES[7:0] bit field is transferred.
Page 960 Inter-integrated circuit (I2C) interface RM0461 By default, the slave uses its clock stretching capability, which means that it stretches the SCL signal at low level when needed, in order to perform software actions. If the master does not support clock stretching, the I2C must be configured with NOSTRETCH = 1 in the I2C_CR1 register.
Page 961: Figure 268. Slave Initialization Flow
RM0461 Inter-integrated circuit (I2C) interface Slave byte control mode In order to allow byte ACK control in slave reception mode, The Slave byte control mode must be enabled by setting the SBC bit in the I2C_CR1 register. This is required to be compliant with SMBus standards.
Page 962 Inter-integrated circuit (I2C) interface RM0461 Slave transmitter A transmit interrupt status (TXIS) is generated when the I2C_TXDR register becomes empty. An interrupt is generated if the TXIE bit is set in the I2C_CR1 register. The TXIS bit is cleared when the I2C_TXDR register is written with the next data byte to be transmitted.
Page 963: Figure 269. Transfer Sequence Flow For I2C Slave Transmitter, Nostretch = 0
RM0461 Inter-integrated circuit (I2C) interface Figure 269. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0 Slave transmission Slave initialization I2C_ISR.ADDR stretched Read ADDCODE and DIR in I2C_ISR Optional: Set I2C_ISR.TXE = 1 Set I2C_ICR.ADDRCF I2C_ISR.TXIS Write I2C_TXDR.TXDATA MS19851V2 RM0461 Rev 5 963/1306 1014...
Page 964: Figure 270. Transfer Sequence Flow For I2C Slave Transmitter, Nostretch = 1
Inter-integrated circuit (I2C) interface RM0461 Figure 270. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1 Slave transmission Slave initialization I2C_ISR.STOPF I2C_ISR.TXIS Write I2C_TXDR.TXDATA Optional: Set I2C_ISR.TXE = 1 and I2C_ISR.TXIS=1 Set I2C_ICR.STOPCF MS19852V2 964/1306 RM0461 Rev 5...
Page 965: Figure 271. Transfer Bus Diagrams For I2C Slave Transmitter
RM0461 Inter-integrated circuit (I2C) interface Figure 271. Transfer bus diagrams for I2C slave transmitter legend: Example I2C slave transmitter 3 bytes with 1st data flushed, NOSTRETCH=0: transmission ADDR TXIS TXIS TXIS TXIS reception SCL stretch Address data3 data1 data2 EV4 EV5 EV1: ADDR ISR: check ADDCODE and DIR, set TXE, set ADDRCF EV2: TXIS ISR: wr data1 EV3: TXIS ISR: wr data2...
Page 966: Figure 272. Transfer Sequence Flow For Slave Receiver With Nostretch = 0
Inter-integrated circuit (I2C) interface RM0461 Slave receiver RXNE is set in I2C_ISR when the I2C_RXDR is full, and generates an interrupt if RXIE is set in I2C_CR1. RXNE is cleared when I2C_RXDR is read. When a STOP is received and STOPIE is set in I2C_CR1, STOPF is set in I2C_ISR and an interrupt is generated.
Page 967: Figure 273. Transfer Sequence Flow For Slave Receiver With Nostretch = 1
RM0461 Inter-integrated circuit (I2C) interface Figure 273. Transfer sequence flow for slave receiver with NOSTRETCH = 1 Slave reception Slave initialization I2C_ISR.STOPF I2C_ISR.RXNE Set I2C_ICR.STOPCF Read I2C_RXDR.RXDATA MS19856V2 Figure 274. Transfer bus diagrams for I2C slave receiver legend: Example I2C slave receiver 3 bytes, NOSTRETCH=0: transmission ADDR RXNE...
Page 968 Inter-integrated circuit (I2C) interface RM0461 32.4.9 I2C master mode I2C master initialization Before enabling the peripheral, the I2C master clock must be configured by setting the SCLH and SCLL bits in the I2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C Configuration window.
Page 969: Figure 275. Master Clock Generation
RM0461 Inter-integrated circuit (I2C) interface Figure 275. Master clock generation SCL master clock generation SCL high level detected SCLH counter starts SCLH SYNC2 SCLL SYNC1 SCL low level detected SCL released SCLL counter starts SCL driven low SCL master clock synchronization SCL high level detected SCL high level detected SCL high level detected...
Page 970: Table 216. I2C-Smbus Specification Clock Timings
Inter-integrated circuit (I2C) interface RM0461 Caution: To be I C or SMBus compliant, the master clock must respect the timings given in the table below. Table 216. I C-SMBus specification clock timings Standard- Fast-mode Fast-mode SMBus mode (Sm) (Fm) Plus (Fm+) Symbol Parameter Unit...
Page 971: Figure 276. Master Initialization Flow
RM0461 Inter-integrated circuit (I2C) interface Note: The START bit is reset by hardware when the slave address has been sent on the bus, whatever the received acknowledge value. The START bit is also reset by hardware if an arbitration loss occurs. In 10-bit addressing mode, when the Slave Address first 7 bits are NACKed by the slave, the master re-launches automatically the slave address transmission until ACK is received.
Page 972: Figure 278. 10-Bit Address Read Access With Head10R = 1
Inter-integrated circuit (I2C) interface RM0461 • If the master addresses a 10-bit address slave, transmits data to this slave and then reads data from the same slave, a master transmission flow must be done first. Then a repeated start is set with the 10 bit slave address configured with HEAD10R = 1. In this case the master sends this sequence: ReStart + Slave address 10-bit header Read.
Page 973: Figure 279. Transfer Sequence Flow For I2C Master Transmitter For N≤255 Bytes
RM0461 Inter-integrated circuit (I2C) interface Figure 279. Transfer sequence flow for I2C master transmitter for N≤255 bytes Master transmission Master initialization NBYTES = N AUTOEND = 0 for RESTART; 1 for STOP Configure slave address Set I2C_CR2.START I2C_ISR.TXIS I2C_ISR.NACKF = Write I2C_TXDR NBYTES transmitted?
Page 974: Figure 280. Transfer Sequence Flow For I2C Master Transmitter For N>255 Bytes
Inter-integrated circuit (I2C) interface RM0461 Figure 280. Transfer sequence flow for I2C master transmitter for N>255 bytes Master transmission Master initialization NBYTES = 0xFF; N=N-255 RELOAD = 1 Configure slave address Set I2C_CR2.START I2C_ISR.TXIS I2C_ISR.NACKF = 1? = 1? Write I2C_TXDR NBYTES transmitted I2C_ISR.TC...
Page 975: Figure 281. Transfer Bus Diagrams For I2C Master Transmitter
RM0461 Inter-integrated circuit (I2C) interface Figure 281. Transfer bus diagrams for I2C master transmitter Example I2C master transmitter 2 bytes, automatic end mode (STOP) legend: TXIS TXIS transmission reception Address data1 data2 SCL stretch INIT EV1 EV2 NBYTES INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START EV1: TXIS ISR: wr data1 EV2: TXIS ISR: wr data2 Example I2C master transmitter 2 bytes, software end mode (RESTART)
Page 976 Inter-integrated circuit (I2C) interface RM0461 Master receiver In the case of a read transfer, the RXNE flag is set after each byte reception, after the eighth SCL pulse. An RXNE event generates an interrupt if the RXIE bit is set in the I2C_CR1 register.
Page 977: Figure 282. Transfer Sequence Flow For I2C Master Receiver For N≤255 Bytes
RM0461 Inter-integrated circuit (I2C) interface Figure 282. Transfer sequence flow for I2C master receiver for N≤255 bytes Master reception Master initialization NBYTES = N AUTOEND = 0 for RESTART; 1 for STOP Configure slave address Set I2C_CR2.START I2C_ISR.RXNE Read I2C_RXDR NBYTES received? I2C_ISR.TC =...
Page 978: Figure 283. Transfer Sequence Flow For I2C Master Receiver For N >255 Bytes
Inter-integrated circuit (I2C) interface RM0461 Figure 283. Transfer sequence flow for I2C master receiver for N >255 bytes Master reception Master initialization NBYTES = 0xFF; N=N-255 RELOAD =1 Configure slave address Set I2C_CR2.START I2C_ISR.RXNE Read I2C_RXDR NBYTES received? I2C_ISR.TC = Set I2C_CR2.START with slave addess NBYTES ...
Page 979: Figure 284. Transfer Bus Diagrams For I2C Master Receiver
RM0461 Inter-integrated circuit (I2C) interface Figure 284. Transfer bus diagrams for I2C master receiver Example I2C master receiver 2 bytes, automatic end mode (STOP) RXNE RXNE legend: transmission Address data1 data2 reception INIT SCL stretch NBYTES INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START EV1: RXNE ISR: rd data1 EV2: RXNE ISR: rd data2 Example I2C master receiver 2 bytes, software end mode (RESTART)
Page 980: Table 217. Examples Of Timing Settings For Fi2Cclk = 8 Mhz
Inter-integrated circuit (I2C) interface RM0461 32.4.10 I2C_TIMINGR register configuration examples The tables below provide examples of how to program the I2C_TIMINGR to obtain timings compliant with the I C specification. In order to get more accurate configuration values, the STM32CubeMX tool (I2C Configuration window) must be used. Table 217.
Page 981 RM0461 Inter-integrated circuit (I2C) interface 2. t minimum value is 4 x t = 250 ns. Example with t = 1000 ns. SYNC1 + SYNC2 I2CCLK SYNC1 + SYNC2 minimum value is 4 x t = 250 ns. Example with t = 750 ns.
Page 982 Inter-integrated circuit (I2C) interface RM0461 Received command and data acknowledge control A SMBus receiver must be able to NACK each received command or data. In order to allow the ACK control in slave mode, the Slave Byte Control mode must be enabled by setting SBC bit in I2C_CR1 register.
Page 983: Table 219. Smbus Timeout Specifications
RM0461 Inter-integrated circuit (I2C) interface Timeouts This peripheral embeds hardware timers in order to be compliant with the three timeouts defined in SMBus specification. Table 219. SMBus timeout specifications Limits Symbol Parameter Unit Detect clock low timeout TIMEOUT Cumulative clock low extend time (slave device) LOW:SEXT Cumulative clock low extend time (master device) LOW:MEXT...
Page 984 Inter-integrated circuit (I2C) interface RM0461 Bus idle detection A master can assume that the bus is free if it detects that the clock and data signals have been high for t greater than t . (refer to Table 214) IDLE HIGH This timing parameter covers the condition where a master has been dynamically added to the bus and may not have detected a state transition on the SMBCLK or SMBDAT lines.
Page 985: Table 220. Smbus With Pec Configuration
RM0461 Inter-integrated circuit (I2C) interface Table 220. SMBus with PEC configuration Mode SBC bit RELOAD bit AUTOEND bit PECBYTE bit Master Tx/Rx NBYTES + PEC+ STOP Master Tx/Rx NBYTES + PEC + ReSTART Slave Tx/Rx with PEC Timeout detection The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the I2C_TIMEOUTR register.
Page 986: Table 221. Examples Of Timeouta Settings For Various I2Cclk Frequencies
Inter-integrated circuit (I2C) interface RM0461 SMBus: 32.4.13 I2C_TIMEOUTR register configuration examples This section is relevant only when SMBus feature is supported. Refer to Section 32.3: I2C implementation. • Configuring the maximum duration of t to 25 ms: TIMEOUT Table 221. Examples of TIMEOUTA settings for various I2CCLK frequencies (max t = 25 ms) TIMEOUT...
Page 987: Figure 286. Transfer Sequence Flow For Smbus Slave Transmitter N Bytes + Pec
RM0461 Inter-integrated circuit (I2C) interface Figure 286. Transfer sequence flow for SMBus slave transmitter N bytes + PEC SMBus slave transmission Slave initialization I2C_ISR.ADDR = Read ADDCODE and DIR in I2C_ISR stretched I2C_CR2.NBYTES = N + 1 PECBYTE=1 Set I2C_ICR.ADDRCF I2C_ISR.TXIS Write I2C_TXDR.TXDATA MS19867V2...
Page 988 Inter-integrated circuit (I2C) interface RM0461 SMBus Slave receiver When the I2C is used in SMBus mode, SBC must be programmed to ‘1’ in order to allow the PEC checking at the end of the programmed number of data bytes. In order to allow the ACK control of each byte, the reload mode must be selected (RELOAD=1).
Page 989: Figure 288. Transfer Sequence Flow For Smbus Slave Receiver N Bytes + Pec
RM0461 Inter-integrated circuit (I2C) interface Figure 288. Transfer sequence flow for SMBus slave receiver N Bytes + PEC SMBus slave reception Slave initialization I2C_ISR.ADDR = Read ADDCODE and DIR in I2C_ISR stretched I2C_CR2.NBYTES = 1, RELOAD =1 PECBYTE=1 Set I2C_ICR.ADDRCF I2C_ISR.RXNE =1? I2C_ISR.TCR = 1? Read I2C_RXDR.RXDATA...
Page 990: Figure 289. Bus Transfer Diagrams For Smbus Slave Receiver (Sbc=1)
Inter-integrated circuit (I2C) interface RM0461 Figure 289. Bus transfer diagrams for SMBus slave receiver (SBC=1) legend: Example SMBus slave receiver 2 bytes + PEC transmission ADDR RXNE RXNE RXNE reception Address data1 data2 SCL stretch NBYTES EV1: ADDR ISR: check ADDCODE and DIR, program NBYTES = 3, PECBYTE=1, RELOAD=0, set ADDRCF EV2: RXNE ISR: rd data1 EV3: RXNE ISR: rd data2 EV4: RXNE ISR: rd PEC...
Page 991: Figure 290. Bus Transfer Diagrams For Smbus Master Transmitter
RM0461 Inter-integrated circuit (I2C) interface When the SMBus master wants to send a RESTART condition after the PEC, software mode must be selected (AUTOEND=0). In this case, once NBYTES - 1 have been transmitted, the I2C_PECR register content is transmitted and the TC flag is set after the PEC transmission, stretching the SCL line low.
Page 992 Inter-integrated circuit (I2C) interface RM0461 SMBus master receiver When the SMBus master wants to receive the PEC followed by a STOP at the end of the transfer, automatic end mode can be selected (AUTOEND = 1). The PECBYTE bit must be set and the slave address must be programmed, before setting the START bit.
Page 993: Figure 291. Bus Transfer Diagrams For Smbus Master Receiver
RM0461 Inter-integrated circuit (I2C) interface Figure 291. Bus transfer diagrams for SMBus master receiver Example SMBus master receiver 2 bytes + PEC, automatic end mode (STOP) RXNE RXNE RXNE legend: transmission data1 data2 Address reception INIT SCL stretch NBYTES INIT: program Slave address, program NBYTES = 3, AUTOEND=1, set PECBYTE, set START EV1: RXNE ISR: rd data1 EV2: RXNE ISR: rd data2 EV3: RXNE ISR: rd PEC...
Page 994 Inter-integrated circuit (I2C) interface RM0461 32.4.15 Wakeup from Stop mode on address match This section is relevant only when wakeup from Stop mode feature is supported. Refer to Section 32.3: I2C implementation. The I2C is able to wakeup the MCU from Stop mode (APB clock is off), when it is addressed.
Page 995 RM0461 Inter-integrated circuit (I2C) interface Arbitration lost (ARLO) An arbitration loss is detected when a high level is sent on the SDA line, but a low level is sampled on the SCL rising edge. • In master mode, arbitration loss is detected during the address phase, data phase and data acknowledge phase.
Page 996 Inter-integrated circuit (I2C) interface RM0461 When a timeout violation is detected in master mode, a STOP condition is automatically sent. When a timeout violation is detected in slave mode, SDA and SCL lines are automatically released. When a timeout error is detected, the TIMEOUT flag is set in the I2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
Page 997: Table 224. Effect Of Low-Power Modes On The I2C
RM0461 Inter-integrated circuit (I2C) interface DMA must be initialized before setting the START bit. The end of transfer is managed with the NBYTES counter. • In Slave mode with NOSTRETCH = 0, when all data are transferred using DMA, the DMA must be initialized before the address match event, or in the ADDR interrupt subroutine, before clearing the ADDR flag.
Page 998: Table 225. I2C Interrupt Requests
Inter-integrated circuit (I2C) interface RM0461 32.6 I2C interrupts The table below gives the list of I2C interrupt requests. Table 225. I2C Interrupt requests Exit the Exit the Exit the Stop 0, Interrupt Interrupt Event Enable Interrupt clear Standby, Sleep Stop 1, acronym event flag...
Page 999 RM0461 Inter-integrated circuit (I2C) interface 32.7 I2C registers Refer to Section 1.2 on page 55 for a list of abbreviations used in register descriptions. The peripheral registers are accessed by words (32-bit). 32.7.1 I2C control register 1 (I2C_CR1) Address offset: 0x00 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing.
Page 1000 Inter-integrated circuit (I2C) interface RM0461 Bit 19 GCEN: General call enable 0: General call disabled. Address 0b00000000 is NACKed. 1: General call enabled. Address 0b00000000 is ACKed. Bit 18 WUPEN: Wakeup from Stop mode enable 0: Wakeup from Stop mode disable. 1: Wakeup from Stop mode enable.