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RM0091
28.7.3
CEC Tx data register (CEC_TXDR)
Address offset: 0x8
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 TXD[7:0]: Tx Data register.
TXD is a write-only register containing the data byte to be transmitted.
Note: TXD must be written when TXSTART=1
28.7.4
CEC Rx Data Register (CEC_RXDR)
Address offset: 0xC
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 RXD[7:0]: Rx Data register.
RXD is read-only and contains the last data byte which has been received from the CEC line.
28.7.5
CEC Interrupt and Status Register (CEC_ISR)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
ACKE
rc_w1
Bits 31:13 Reserved, must be kept at reset value.
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
TX
TX
TX
TX
ERR
UDR
END
rc_w1
rc_w1
rc_w1
Doc ID 018940 Rev 1
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
w
w
w
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
r
r
r
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
ARB
RX
TXBR
LBPE
LST
ACKE
rc_w1
rc_w1
rc_w1
rc_w1
HDMI-CEC controller (HDMI-CEC)
20
19
18
Res.
Res.
Res.
4
3
2
TXD[7:0]
w
w
w
20
19
18
Res.
Res.
Res.
4
3
2
RXD[7:0]
r
r
r
20
19
18
Res.
Res.
Res.
5
4
3
2
RX
SBPE
BRE
OVR
rc_w1
rc_w1
rc_w1
17
16
Res.
Res.
1
0
w
w
17
16
Res.
Res.
1
0
r
r
17
16
Res.
Res.
1
0
RX
RXBR
END
rc_w1
rc_w1
713/742
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