Exti Registers; Interrupt Mask Register (Exti_Imr); Event Mask Register (Exti_Emr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
11.3 registers
EXTI
Refer to
The peripheral registers have to be accessed by words (32-bit).
11.3.1

Interrupt mask register (EXTI_IMR)

Address offset: 0x00
Reset value: 0x0F94 0000 (See note below)
31 30 29
Res. Res. Res. Res.
15 14 13
MR15 MR14 MR13 MR12
rw rw rw
Bits 31:28 Reserved, must be kept at reset value (0).
Bits 27:0 MRx: Interrupt Mask on external/internal line x
Note: The reset value for the internal lines (18, 20, 23, 24, 25, 26 and 27) is set to '1' in order to
enable the interrupt by default.
11.3.2

Event mask register (EXTI_EMR)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
MR15 MR14 MR13 MR12
rw rw rw
Bits 31:28 Reserved, must be kept at reset value (0).
Bits 27:0 MRx: Event mask on external/internal line x
Section 1.1 on page 34
28 27 26 25
MR27 MR26 MR25
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12 11 10 9
MR11 MR10 MR9
rw rw rw rw
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
28 27 26 25
MR27 MR26 MR25
rw rw rw
12 11 10 9
MR11 MR10 MR9
rw rw rw rw
0: Event request from Line x is masked
1: Event request from Line x is not masked
Doc ID 018940 Rev 1
for a list of abbreviations used in register descriptions.
24 23 22
MR24 MR23 MR22 MR21
rw rw rw
8 7 6
MR8 MR7 MR6 MR5
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24 23 22
MR24 MR23 MR22 MR21
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8 7 6
MR8 MR7 MR6 MR5
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Interrupts and events
21 20 19 18
MR20 MR19 MR18
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5 4 3 2
MR4 MR3 MR2
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21 20 19 18
MR20 MR19 MR18
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5 4 3 2
MR4 MR3 MR2
rw rw rw rw
17 16
MR17 MR16
rw rw
1 0
MR1 MR0
rw rw
17 16
MR17 MR16
rw rw
1 0
MR1 MR0
rw rw
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