Counter Modes; Figure 154. Counter Timing Diagram With Prescaler Division Change From 1 To 2; Figure 155. Counter Timing Diagram With Prescaler Division Change From 1 To 4 - STMicroelectronics STM32F05 series Reference Manual

General-purpose timers (TIM15/16/17)

Figure 154. Counter timing diagram with prescaler division change from 1 to 2

Figure 155. Counter timing diagram with prescaler division change from 1 to 4

18.4.2

Counter modes

Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is
repeated for the number of times programmed in the repetition counter register
(TIMx_RCR). Else the update event is generated at each counter overflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
380/742
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Update event (UEV)
Prescaler control register
Write a new value in TIMx_PSC
Prescaler buffer
Prescaler counter
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Update event (UEV)
Prescaler control register
Write a new value in TIMx_PSC
Prescaler buffer
Prescaler counter
Doc ID 018940 Rev 1
F7 F8 F9 FA FB FC 00
0
0
0 0 1
F7 F8 F9 FA FB FC
0
0
0 1
0
RM0091
01 02 03
1
1
0 1 0 1 0 1
00 01
3
3
2 3 0 1 2 3