Repetition Counter - STMicroelectronics STM32F05 series Reference Manual

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Figure 161. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
18.4.3

Repetition counter

Section 17.3.1: Time-base unit
respect to the counter overflows/underflows. It is actually generated only when the repetition
counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N counter overflows or underflows,
where N is the value in the TIMx_RCR repetition counter register.
The repetition counter is decremented at each counter overflow in upcounting mode.
The repetition counter is an auto-reload type; the repetition rate is maintained as defined by
the TIMx_RCR register value (refer to
software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave
mode controller, it occurs immediately whatever the value of the repetition counter is and the
repetition counter is reloaded with the content of the TIMx_RCR register.
preloaded)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Auto-reload shadow register
Write a new value in TIMx_ARR
describes how the update event (UEV) is generated with
Doc ID 018940 Rev 1
General-purpose timers (TIM15/16/17)
F0 F1 F2 F3 F4 F5 00
F5
F5
Figure 162). When the update event is generated by
01 02 03 04 05 06 07
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