STMicroelectronics STM32F05 series Reference Manual page 602

Universal synchronous asynchronous receiver transmitter (USART)
encoded. While receiving data, transmission should be avoided as the data to be
transmitted could be corrupted.
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A 0 is transmitted as a high pulse and a 1 is transmitted as a 0. The width of the pulse
is specified as 3/16th of the selected bit period in normal mode (see
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The SIR decoder converts the IrDA compliant receive signal into a bit stream for
USART.
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The SIR receive logic interprets a high state as a logic one and low pulses as logic
zeros.
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The transmit encoder output has the opposite polarity to the decoder input. The SIR
output is in low state when Idle.
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The IrDA specification requires the acceptance of pulses greater than 1.41 µs. The
acceptable pulse width is programmable. Glitch detection logic on the receiver end
filters out pulses of width less than 2 PSC periods (PSC is the prescaler value
programmed in the USART_GTPR register). Pulses of width less than 1 PSC period
are always rejected, but those of width greater than one and less than two periods may
be accepted or rejected, those greater than 2 periods will be accepted as a pulse. The
IrDA encoder/decoder doesn't work when PSC=0.
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The receiver can communicate with a low-power transmitter.
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In IrDA mode, the STOP bits in the USART_CR2 register must be configured to "1 stop
bit".
602/742 Doc ID 018940 Rev 1
RM0091
Figure 246).