Figure 97. Counter Timing Diagram, Internal Clock Divided By N; Figure 98. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded) - STMicroelectronics STM32F05 series Reference Manual

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Figure 97. Counter timing diagram, internal clock divided by N

Figure 98. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not
CK_INT
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
preloaded)
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
Write a new value in TIMx_ARR
Doc ID 018940 Rev 1
General-purpose timers (TIM2 and TIM3)
1F
20
31 32 33 34 35 36 00 01 02 03 04 05 06 07
FF
00
36
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