Receiver; Table 27. Sub-Ghz Radio Transmit High Output Power; Figure 11. Low Output Power Pa - STMicroelectronics STM32WL5 Series Reference Manual

Sub-GHz radio (SUBGHZ)
Table 27
Transmitter low output power
The transmit low output power up to + 15 dBm, is supported through the RFO_LP pin. The
LP PA can be supplied from the PA regulator (REG PA) up to 1.35 V. For this, the REG PA
must be supplied from the regulated V
below.
The output power range is programmable in 32 steps of ~1 dB. The power amplifier ramping
timing is also programmable.This allows adaptation to meet radio regulation requirements.
LDO/SMPS
5.3.4

Receiver

The receive chain comprises a differential low-noise amplifier (LNA), a down-converter to
low-IF by mixer operation in quadrature configuration. The I and Q signals are low pass
filtered and a Ʃ∆ ADC converts them into the digital domain. In the digital modem, the
signals are decimated, further down converted and channel filtered. The demodulation is
done according to the selected modulation scheme.
The down mixing to low-IF is done by mixing the receive signal with the local RF-PLL
located in the negative frequency, where -f
158/1450
gives the maximum transmit output power versus the V

Table 27. Sub-GHz radio transmit high output power

V supply (V)
DDPA
3.3
2.7
2.4
1.8

Figure 11. Low output power PA

LDO mode
V
DD
VDDSMPS (1.8 to 3.6V)
REG
PA
LP PA
Note: Use of the SMPS is optional. When SMPS is not used, the BOM can be reduced by removing the coil
between VLXSMPS and VFBSMPS pins.
Transmit output power (dBm)
supply at 1.55 V, as shown in the figure
FBSMPS
VLXSMPS
LDO/SMPS
VFBSMPS (1.55V)
VDDPA
VR_PA (up to 1.35V)
RFO_LP
= -f + f
lo rf
RM0453 Rev 5
supply level.
DDPA
+ 22
+ 20
+ 19
+ 16
SMPS mode
V
DD
VDDSMPS (1.8 to 3.6V)
VLXSMPS
VFBSMPS (1.55V)
VDDPA
VR_PA (up to 1.35V)
REG
PA
RFO_LP
LP PA
. (where f is the local RF-PLL
if lo
RM0453
MSv62617V2