Figure 100. Counter Timing Diagram, Internal Clock Divided By 1; Figure 101. Counter Timing Diagram, Internal Clock Divided By 2; Figure 102. Counter Timing Diagram, Internal Clock Divided By 4 - STMicroelectronics STM32F05 series Reference Manual

RM0091

Figure 100. Counter timing diagram, internal clock divided by 1

Figure 101. Counter timing diagram, internal clock divided by 2

Figure 102. Counter timing diagram, internal clock divided by 4

CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow (cnt_udf)
Update event (UEV)
Update interrupt flag (UIF)
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Doc ID 018940 Rev 1
General-purpose timers (TIM2 and TIM3)
05 04 03 02 01 00 36 35 34 33 32 31 30 2F
0002 0001 0000 0036 0035 0034 0033
0001 0000 0036 0035
299/742