Once Global Data Bus Register (Ogdb) - Freescale Semiconductor Symphony DSP56724 Reference Manual

limit to be placed on the number of cycles that the DMA is stalled, due to internal memory contention for
a single DMA memory access.
• When the DMA Stall Register is set to zero, the DMA Stall Interrupt is disabled.
• When the DMA Stall Register is set to a non-zero value, a stall counter will keep track of the
number of cycles the DMA is stalled due to internal memory contention for a single memory
access. If the stall counter is ever larger than the value stored in the DMA Stall Register, the DMA
Stall non-maskable Interrupt will be asserted.
• The DMA Stall Interrupt remains asserted until the internal memory contention ends (usually due
to the interrupt routine) or until the DMA Stall Register is written with zero. The stall counter clears
when the internal memory contention ends or when the DMA Stall Register is written with zero.
DMA Stall R
Register D23
W
(DMAS)
R
D11
W
6.2.3

OnCE Global Data Bus Register (OGDB)

The OnCE GDB Register is 24-bit read/write register that can be read through the JTAG port, and is used
for passing data between the chip and an external command controller.
OnCE GDB R
O23
Register
W
(OGDB)
R
O11
W
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
Table 6-7. DMA Stall Register (DMAS)
23 22 21 20
11 10 9 8
D22 D21 D20
D10 D9 D8
Table 6-8. OnCE GDB Register (OGDB)
23 22 21 20
11 10 9 8
O22 O21 O20
O10 O9 O8
Core Integration Module (CIM, CIM_1)
19 18 17 16
7 6 5
D19 D18 D17 D16
D7 D6 D5 D4
19 18 17 16
7 6 5
O19 O18 O17 O16
O7 O6 O5 O4
15 14 13
4 3 2 1
D15 D14 D13
D3 D2 D1
15 14 13
4 3 2 1
O15 O14 O13
O3 O2 O1
12
0
D12
D0
12
0
O12
O0
6-5