ST STM32L4+ Series Reference Manual page 1282

Advanced-control timers (TIM1/TIM8)
Bit 28 BKBID: Break Bidirectional
0: Break input BRK in input mode
1: Break input BRK in bidirectional mode
In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input
mode and in open drain output mode. Any active break event asserts a low logic level on the
Break input to indicate an internal break event to external devices.
Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 27 BK2DSRM: Break2 Disarm
Refer to BKDSRM description
Bit 26 BKDSRM: Break Disarm
0: Break input BRK is armed
1: Break input BRK is disarmed
This bit is cleared by hardware when no break source is active.
The BKDSRM bit must be set by software to release the bidirectional output control (open-
drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the
fault condition has disappeared.
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 25 BK2P: Break 2 polarity
0: Break input BRK2 is active low
1: Break input BRK2 is active high
Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 24 BK2E: Break 2 enable
This bit enables the complete break 2 protection (including all sources connected to bk_acth
and BKIN sources, as per
0: Break2 function disabled
1: Break2 function enabled
Note: The BKIN2 must only be used with OSSR = OSSI = 1.
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
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in TIMx_BDTR register).
in TIMx_BDTR register).
Figure 327: Break and Break2 circuitry
TIMx_BDTR register).
RM0432 Rev 6
RM0432
overview).