ST STM32L4+ Series Reference Manual page 1280

Advanced-control timers (TIM1/TIM8)
37.4.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 1, 8)
Address offset: 0x38
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 CCR2[15:0]: Capture/Compare 2 value
37.4.18 TIMx capture/compare register 3 (TIMx_CCR3)(x = 1, 8)
Address offset: 0x3C
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 CCR3[15:0]: Capture/Compare value
If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual
capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC3 output.
If channel CC3 is configured as input: CCR3 is the counter value transferred by the last
input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be
programmed.
1280/2301
12 11 10 9
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If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual
capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC2 output.
If channel CC2 is configured as input: CCR2 is the counter value transferred by the last
input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be
programmed.
12 11 10 9
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8 7 6
CCR2[15:0]
rw rw rw
8 7 6
CCR3[15:0]
rw rw rw
RM0432 Rev 6
5 4 3 2
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5 4 3 2
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RM0432
1 0
rw rw
1 0
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