ST STM32L4+ Series Reference Manual page 1278

Advanced-control timers (TIM1/TIM8)
37.4.12 TIMx counter (TIMx_CNT)(x = 1, 8)
Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
UIF
Res. Res. Res.
CPY
r
15 14 13
rw rw rw
Bit 31 UIFCPY: UIF copy
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value
37.4.13 TIMx prescaler (TIMx_PSC)(x = 1, 8)
Address offset: 0x28
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
37.4.14 TIMx auto-reload register (TIMx_ARR)(x = 1, 8)
Address offset: 0x2C
Reset value: 0xFFFF
15 14 13
rw rw rw
Bits 15:0 ARR[15:0]: Auto-reload value
1278/2301
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in
the TIMxCR1 is reset, bit 31 is reserved and read at 0.
12 11 10 9
rw rw rw rw
The counter clock frequency (CK_CNT) is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in "reset mode").
12 11 10 9
rw rw rw rw
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 37.3.1: Time-base unit on page 1199
update and behavior.
The counter is blocked while the auto-reload value is null.
24 23 22
Res. Res. Res.
8 7 6
CNT[15:0]
rw rw rw
8 7 6
PSC[15:0]
rw rw rw
8 7 6
ARR[15:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
5 4 3 2
rw rw rw rw
/ (PSC[15:0] + 1).
CK_PSC
5 4 3 2
rw rw rw rw
for more details about ARR
RM0432
17 16
Res. Res.
1 0
rw rw
1 0
rw rw
1 0
rw rw